Addressing technique employing both direct and indirect register addressing
AssigneeSanders Associates, Inc.
InventorHoward W. Edwards, Jr.
Life of this patent
Estimating the term…
Abstract
A serial buss processor with detailed description of program branching and register addressing. A mask and branch instruction is utilized to effect a relative program branch of up to N + 1 address locations away from the address of the current or masking branch instruction, where N is the number of bits in the data operand. Register addressing is partly direct and partly indirect. The indirect register address scheme employs a directly addressable register, the contents of which are interpreted by an indirect address generator unit which itself is directly addressable such that a single value in the directly addressable register may be used to point to different registers.
Claims4
In a buss type processor in which a direct address generator generates a pair of direct addresses for addressing one of a first plurality of registers in response to an address field contained within the processor instruction set;
- the improvement comprising
- a second plurality of registers each accessed by a pair of indirect addresses,
- first and second multiplexers jointly responsive to the contents of said one of said first plurality of registers and to said pair of direct addresses to select a portion of the contents of said one of said first plurality of registers, and
- first and second decoders jointly responsive to said portion of the contents of said one of said first plurality of registers selected by said first and second multiplexers to generate a pair of indirect addresses to address one of said second plurality of registers.
In a buss type processor in which a direct address generator generates a pair of direct addresses for addressing one of a first plurality of registers in response to an address field contained within the processor instruction set, the improvement comprising
- a second plurality of registers each accessed by a pair of indirect addresses,
- a first multiplexer responsive either to a first portion of one of said pair of direct addresses and to the contents of a first segment of said addressed one of said first registers, or responsive to a second portion of said one of said pair of direct addresses and to the contents of a second segment of said addressed one of said first registers to generate a first output signal, where said first or said second portion of said addresses are selected by said processor in response to programmed instruction,
- a second multiplexer responsive either to a first portion of the other of said pair of direct addresses and to the contents of said first segment of said addressed one of said first registers or responsive to a second portion of said other of said pair of direct addresses and to the contents of said second segment of said addressed one of said first registers to generate a second output signal, where said first or said second portion of said addresses are selected by said processor in response to programmed instructions,
- a first decoder responsive to said first output signal to generate a first plurality of indirect addresses to address ones of a first group of said second plurality of registers, and
- a second decoder responsive to said second output signal to generate a second plurality of indirect addresses to address ones of a second group of said second plurality of registers.
Dependencies are inferred from the claim text.