Dispersion compensated circuitry for analog charged systems
AssigneeTexas Instruments Incorporated
InventorDennis Darcy Buss
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Abstract
Circuitry for compensating for charge transfer inefficiency related dispersion in analog charge transfer devices (CTD's) is disclosed. In one aspect of the invention the tap weights of a filter are modified in a preselected manner to provide dispersion correction. In a different configuration, a dispersion compensating filter is connected to the input of a charge transfer delay line to provide an initial signal which is the inverse of the total dispersion of the CTD. In a further aspect of the invention regenerators are inserted into a CTD delay line to provide negative feedback to previous stages of the delay line in order to compensate for dispersion.
Claims8
A charge transfer device analog delay line having a series of delay stages, each characterized by a predetermined delay and means for shifting input signals between said delay stages, said delay line having an output substantially free from charge transfer loss dispersion, comprising:
- input means connected to said delay line for receiving input signals and for applying said input signals to a first delay stage of said delay line;
- first circuit means connected to said input means for generating, responsive to a said input signal, a dispersion compensation output singal having an amplitude equal to the inverse of the total dispersion of said delay line;
- and
- second circuit means operable to delay said dispersion compensation output signal and to apply said delayed dispersion compensation output signal to said first delay stage of said delay line delayed by said predetermined delay relative to application of said input signal by said input means to said first delay stage of said delay line for combination with an input signal at said first delay stage.
A charge transfer device analog delay line having a plurality of charge storage nodes and means for shifting input signals between said storage nodes, said delay line having an output signal substantially free from charge transfer loss dispersion comprising:
- amplifier means for non-destructively sampling the signal at a selected storage node of said shift register and combining said sampled signal with an input signal at a preceding shift register storage node, said amplifier having a preselected gain effective to cancel the trailing edge dispersion signal components to first order in loss.
A charge-transfer device analog delay line having a plurality of charge storage nodes and means for shifting input signals between said storage nodes, said delay line characterized by a predetermined charge dispersion during shifting of said input signals between said storage nodes, and having an output substantially free from dispersion, comprising:
- correction circuit means having input means connected to at least one of said storage nodes for generating a correction signal related to the signals at said one storage node, and having output means connected to at least one other of said storage nodes for applying said correction signal to said other storage node for modifying said shifted signals by a correction factor to substantially cancel charge dispersion from the output from said delay line.
A charge transfer device analog delay line including an input node, an output node, and a plurality of charge storage nodes defined between said input node and said output node, and means for shifting input signals between said storage nodes from said input node to said output node, said delay line characterized by a predetermined charge dispersion during shifting of said input signals between said storage nodes, comprising:
- dispersion compensation means including means for non-destructive detection of signals at said input node, and signal weighting means connected to apply a weighted signal derived from said means for detection to at least one of said charge storage nodes for modifying said shifted signals by a correction factor to compensate for charge dispersion at said output node.
Dependencies are inferred from the claim text.