Multiple purpose electronic counting system

An electrical counting circuit comprising a bank of a plurality of multiple decade BCD storage registers collectively providing a plurality of BCD decade sets, each comprising a BCD storage decade of each of the plurality of BCD storage registers, sequencing means for activating the BCD storage decades of each BCD decade set together and activating the BCD decade sets in a predetermined sequence, each multiple decade BCD storage register having a BCD input for entering a BCD count into the active BCD decade of the storage register and a BCD output for reading the BCD count of the active BCD decade, input connector means for transmitting input signals to the electrical counting circuit, and input signal operated control circuit means connected to the input connector means comprising write control means for each BCD storage register selectively operable for writing the respective BCD input into the active BCD decade of the storage register, an arithmetic unit having a BCD input and a BCD output and selectively operable to provide an incremented BCD output count of the BCD input count thereof and hold any resultant carry for a succeeding incremented count operation of the arithmetic unit, and arithmetic unit selector means for selectively operatively connecting the arithmetic unit to each storage register for selectively incrementing the count of each BCD decade thereof, the input signal operated control circuit means being operable by a count input train of count input signals applied to the input connector means to operate the arithmetic unit and arithmetic unit selector means in synchronism with the sequencing means to increment the count of a first storage register with each count input signal means, and being selectively operable by BCD entry signals applied to the input connector means to selectively enter a BCD count into each BCD decade of a second of said BCD storage registers and being selectively operable by increment entry signals applied to the input connector means to operate the arithmetic unit and arithmetic unit selector means is synchronism with the sequencing means to selectively increment the BCD count of each BCD decade of said second storage register.

An electrical counting circuit comprising an integrated solid state circuit portion with at least one multiple decade BCD storage register with a plurality of BCD storage decades for storing BCD counts therein, decade operating means for sequentially activating the BCD storage decades of each BCD storage register and read the BCD count of and write a BCD count into the active BCD storage decade, an arithmetic unit selectively operable with the decade operating means to increment the BCD count of the active BCD storage decade of each BCD storage register and hold any resulting carry for incrementing the BCD count of the succeeding active decade of the storage register, entry connector means, and decade selector means connected to the entry connector means and selectively operable by entry input signals applied to the entry connector means for selectively operating the arithmetic unit with the decade operating means to increment the count of selected BCD decades of each storage register;

• and an entry circuit portion connected to the entry connector means of the solid state circuit portion for applying entry input signals thereto, the entry circuit portion comprising BCD count entry means operable for applying to the entry connector means, a BCD count entry signal for at least one of the BCD decades in synchronism with the activation thereof for operating the decade operating means for writing the BCD count of the BCD count entry signal into the BCD decade, and increment entry means operable for applying to the entry connector means an increment signal for at least one of the BCD decades in synchronism with the activation thereof for operating the decade selector means with the arithmetic unit for incrementing the BCD count of the BCD decade.

An electrical core counting circuit comprising an integrated circuit portion with a plurality of BCD storage registers, each having a plurality of BCD storage words for storing a plurality of BCD counts therein, sequencing means for activating the storage words of each BCD storage register in a predetermined sequence, write means selectively operable for writing a BCD count into the active storage word of each storage register, entry connector means, and input signal operated control means selectively operable by entry signals applied to the entry connector means for selectively operating the write means for writing a BCD count established by the entry signals into each BCD storage register word;

• and an entry circuit portion connected to the entry connector means of the solid state circuit portion for supplying entry signals thereto, the entry circuit portion comprising BCD switch means operable for generating BCD count entry signals for at least one word of each storage register, and entry select means selectively operable for generating storage register word select signals for individually selecting the words of each storage register for entry of a BCD count therein with the corresponding BCD count entry signals;
• the input signal operated control means of the integrated circuit portion being operable by the word select signals and the BCD count entry signals to operate the write means for writing the BCD count entry signals into the respective storage register decade.

An integrated solid state core counting circuit comprising count storage means with a plurality of multiple decade BCD storage registers collectively providing a plurality of BCD decade sets composed of corresponding BCD decades of the plurality of BCD storage registers respectively, core circuit input connector means for transmitting input signals to the core circuit;

• and input signal operated control circuit means connected to the input connector means and selectively operable by partitioning input signals applied to the input connector means for selectively operationally dividing the count storage means into two operationally separate sections thereof, each comprising a BCD storage register section of each of the plurality of BCD storage registers and a selective number of BCD decade sets;
• the input signal operated control circuit means being selectively operable by count entry signals applied to the input connector means for selectively entering a count in each storage register section of a first of said BCD storage registers, and being selectively operable by two separate count input trains of count input signals, applied to the input connector means, for the two separate sections respectively of a second of said storage registers for accumulating separate counts in the respective second storage register sections by stepping the accumulated count of each second storage register section with each respective count input signal, the input signal operated control circuit means being selectively operable by latch select and reset input signals applied to the input connector means for selectively resetting one of said two second storage register sections and simultaneously transfer the count of said one second storage register section to the corresponding first storage register section.

An integrated solid state core counting circuit comprising count storage means with a plurality of multiple decade BCD storage registers providing a plurality of BCD decade sets of corresponding BCD storage decades of the BCD storage registers respectively, core circuit input connector means for transmitting input signals to the core circuit;

• and input signal operated control circuit means connected to the input connector means and selectively operable by partitioning input signals applied to the input connector means for selectively operationally dividing the count storage means into at least two operationally separate sections thereoff, each comprising sections of said plurality of registers respectively, with selective numbers of BCD decade sets respectively, and input signal operated control circuit means being adapted to be selectively alternatively set by multiply/non-multiply select control signals applied to the input connector means to multiplication and non-multiplication modes of operation, the input signal operated control circuit means in its non-multiplication mode being selectively operable by entry input signals applied to the input connector means for selectively entering a count into each storage register section of a first of said storage registers, and being selectively operable by a plurality of external count input trains of relatively low frequency count signals, applied to the input connector means, for the plurality of sections respectively of a second storage register for accumulating separate counts in the respective second storage register sections by indexing the accumulated count of each second storage register section with each respective count signal, the input signal operated control circuit means in its multiplication mode being operable for a multiplication indexing operation of first and second sections of said second storage register together at a relatively high rate upon the occurrence of each count signal of the count input train for the first section of said second storage register, the input signal operated control circuit means comprising comparator circuit means operable for generating predetermining signals when the accumulated count in the first section of the second storage register equals the count entered into the corresponding first storage register section, the input signal operated control circuit means being operable in its multiplication mode by the predetermining signals for terminating the multiplication indexing operation and resetting the first section of the second storage register to zero.

An electrical core counting circuit comprising count storage means having a plurality of multiple decade BCD storage registers collectively providing a plurality of BCD decade sets, each comprising a plurality of corresponding BCD storage decades of the plurality of BCD storage registers respectively, core circuit input connector means for transmitting input signals to the core circuit;

• and input signal operated control circuit means connected to the input connector means and selectively operable by entry input signals applied to the input connector means for selectively entering a count into a first of said storage registers, and being selectively operable by a count input train of count input signals applied to the input connector means, for accumulating a count in a second of said storage registers by stepping the accumulated count of the second storage register with each count signal, the input signal operated control circuit means comprising comparator circuit means operable to generate a predetermining signal when the second storage register equals the count entered into the first storage register, the input signal operated control circuit means comprising decade sequencing means for activating the corresponding BCD storage decades of each BCD decade set together and activating the BCD decade sets in an ascending order sequence, the count storage means comprising, for each of said BCD storage registers, a BCD input for writing a BCD count into the active BCD decade of the storage register and a BCD output for reading the BCD count of the active BCD decade of the storage register, and the input signal operated control circuit means comprising write control means for each said BCD storage register selectively operable for writing the respective BCD input count into the active BCD decade of the storage register, an arithmetic unit having a BCD input and a BCD output and selectively alternatively operable to provide a BCD output count equal to the BCD input count and to an incremented count thereof and hold any resultant carry for a succeeding increment count operation of the arithmetic unit, and arithmetic unit selector means for selectively operatively connecting the arithmetic unit to the second storage register for incrementing the BCD count of each BCD decade thereof, the input signal operated control circuit means being operable by each count input signal, applied to the input connector means, for stepping the accumulated count of the second storage register by operating the arithmetic unit, arithmetic unit selector means and second register write control means in synchronism with the decade sequencing means to increment the count of the lowest order BCD decade of the second storage register and increment any high order decade of the second register where a carry results from an increment operation of the arithmetic unit for the adjacent lower order decade.