US 3,946,215 A · Pseudo-random code generator

Abstract

A pseudo-random bit generator forms a portion of the pseudo-random code generator, and provides square wave output bits over a defined frequency spectrum on a plurality of parallel output lines. The bits present on a selected number of output lines in sequence define a binary number, which is compared with an accumulated count present in a counter driven by a clock running at a predetermined frequency. A correct comparison resets the counter, shifts the pseudo-random bit generator, and shifts a past-history shift register which contains a portion of the output of the pseudo-random code generator. The output from the past-history shift register, and the square wave output bits on certain other parallel output lines from the random bit generator are applied as inputs to respective logic probability circuits. The logic probability circuits are connected to an output logic circuit, the output of which is the pseudo-random code signal, a series of square waves occurring pseudo-randomly over a frequency spectrum which is adjustable by altering the parameters of the various logic probability circuits.

Claims10

Dependent claims

An apparatus for generating a pseudo-random code signal, comprising:

first circuit means operative to produce a plurality of first output bits which define a pseudo-random sequence;
at least one logic gating means responsive to more than one of said first output bits, said logic gating means providing a logic output bit, said logic output bit and selected other first output bits defining a first count;
clock means generating a clock signal of predetermined frequency;
counter means responsive to said clock signal and operative to count from a reference count;
means operative to compare the count of said counter means with said first count, and to generate a comparator signal in response to an equality therebetween;
means responsive to said comparator signal for resetting said counter means to said reference count;
means coupling said comparator signal to said first circuit means, said first circuit means producing in response to said comparator signal a new pseudo-random bit sequence;
and,
means controlled by said comparator signal to produce successive second output bits defining the pseudo-random code signal.

6 more elements

Dependencies are inferred from the claim text.

Pseudo-random code generator

Life of this patent

Pseudo-random code generator

Life of this patent

Abstract

Claims10