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US 3,946,214 AGranted
Multi-level digital filter
AssigneeRixon, Inc.
InventorsRichard L. Stuart, Arvind M. Bhopale
Life of this patent
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AssigneeRixon, Inc.
InventorsRichard L. Stuart, Arvind M. Bhopale
Estimating the term…
A multi-level digital filter system applicable to modems is provided. The incoming data is read serially into M shift registers and read out in parallel by M further shift registers under the control of an M-bit clock, where M=log.sub.2 N and N is the number of levels. After appropriate conditioning by a logic control circuit, the parallel outputs are filtered separately by M digital shaping filters. The shaping filters each comprise a chain of shift registers the outputs of which are weighted by a resistor network and summed to produce a desired time response, which in an exemplary embodiment is the inverse Fourier transform of an ideal low-pass filter. Summing of the filter outputs produces an N-level signal. Specific examples of three-, four-, five-, six- and eight-level systems are disclosed.
A multilevel digital filter system comprising a first set of shift registers, means including a clock for reading the incoming data serially into said first set of shift registers, means including a second set of shift registers connected to the outputs of said first set of shift registers for reading out the data stored in said first set of shift registers in parallel;
A three-level digital filter system comprising a first set of shift registers, means including a clock for reading the incoming data serially into said first set of shift registers, means including a second set of shift registers connected to the outputs of said first set of shift registers for reading out the data stored in said first set of shift registers in parallel;
An N-level digital filter system, where N=5, 6, or 8, said system comprising a first set of shift registers, means including a clock for reading the incoming data serially into said first set of shift registers;
Dependencies are inferred from the claim text.