Resettable electronic counter employing a calculator chip

In an electronic counter having an integrated solid state calculator circuit including synchronizing circuit means repetitively providing a plurality of sequenced timing signals at a plurality of corresponding output conductor means thereof, and having input conductor means for receiving certain of said timing signals selectively coupled thereto for respectively providing separate input control signals to the circuit for clearing a count therein, for conditioning the circuit to count in particular increments, and for advancing the count by the particular increments established, the improvement wherein said counter includes reset means comprising multi-step electronic sequence counter means selectively coupled to a particular said circuit output conductor means for stepping operation responsive to timing signals received therefrom and having output means providing output signals indicative of various steps thereof, said sequence counter means being selectively conditioned for said stepping operation and coupled to said particular output conductor means of said circuit in response to reset signal means selectively applied thereto and being uncoupled from said particular output conductor means upon reaching a predetermined cut-off step of the counter means control logic means coupled to the circuit output conductor means for said certain timing signals and to certain of said sequence counter output means, said control logic means being responsive to said sequence counter output signals and coupled to said circuit input conductor means for transmitting thereto the timing signal providing said count clearing control signal during one output step of said sequence counter and the timing signal providing said conditioning control signal during another output step of said sequence counter subsequent to said one;

• and count indexing signal logic means receiving count indexing signals and being coupled to said sequence counter output means, to the circuit output conductor means for said certain timing signals and to said circuit input conductor means for selectively connecting the timing signal providing said count advancing control signal to said circuit input conductor means during count indexing input signals occurring after both said one and said another steps of said sequence counter and upon attaining said predetermined cut-off step of said sequence counter.

In an electronic counter having an input circuit for receiving a train of electrical indexing signals for indexing the counter to accumulate a count therein;

• a display register with a plurality of digit indicators of ascending order of significance for displaying a count, control input means for sequentially activating the digit indicators for sequentially entering digit counts therein respectively, and a binary input for receiving binary coded input signals for entering digit counts into the digit indicators respectively;
• and a large scale integrated solid state calculator circuit element comprising an arithmetic and control circuit with register means for storing a plurality of separate multiple digit counts therein, including a selected count entered into the register means and an arithmetic count resulting from an arithmetic operation of the arithmetic and control circuit, and a binary output connected to the binary input of the display register and operable, to sequentially provide binary coded output signals indicative of the digit counts of a count stored in the register means for sequentially entering the digit counts into corresponding digit indicators of the display register respectively, for displaying the count with the display register, synchronizing circuit means for repetitively generating a sequence of timing signals, the synchronizing circuit means being connected to the arithmetic and control circuit and to the control input means of the display register for synchronously entering a count stored in the register means into the display register for display thereby, the arithmetic and control circuit having data entry circuit means and operable by selectively applying timing signals to the data entry circuit means for storing a selected count in the register means and displaying the selected count with the display register, the arithmetic and control circuit being further operable by selectively applying timing signals to the data entry circuit means for entering mathematical operation instruction signals into the arithmetic and control circuit for respectively effecting predetermined mathematical operations between the separate counts stored in the register means and storing in the register means the results of the selected mathematical operation as a new arithmetic count and displaying the new arithmetic count with the display register, and including entering an addition instruction signal for adding the selected count stored in the register means to any arithmetic count stored in the register means and storing, in the register means, the summation thereof as a new arithmetic count and displaying the new arithmetic count with the display register, the arithmetic and control circuit being further operable by selectively applying timing signals to the data entry circuit means for selectively clearing any arithmetic count and any selected count stored in the register means and clearing the display register without clearing the selected count stored in the register means, each said selective application of timing signals to the data entry circuit means requiring at least eight consecutive repetitions of a particular said timing signal;
• the improvement wherein the electronic counter comprises counter reset means having a compound electronic binary sequence counter having a lower order section of at least three stages and a four stage, 16-step higher order section, each of said four higher order stages having a step signal output means for providing a binary step signal corresponding with the sequence step count of said higher order counter section, said sequence counter responsive to a reset signal to attain an initial zeroed condition;
• a reset gate connected to the synchronizing circuit means to receive a predetermined one of the timing signals in each said sequence thereof, to the signal output means of the fourth stage of said higher order counter section, and to the input of said lower order counter section for passing said predetermined one of the timing signals to said sequence counter for stepping operation thereof when said sequence counter is zeroed for sequence counting and for blocking said predetermined one of the timing signals at the eighth step of said higher order counter section to terminate said stepping operation, reset switch means connected to said sequence counter and selectively operable for generating a reset signal for zeroing said sequence counter, and control logic means connected to said synchronizing circuit means, to the step signal output means for each of the first three stages of said sequence counter higher order section, and to the data entry circuit means and operable to selectively apply timing signals to the data entry circuit means during the first and third steps of said higher order counter section for operating the arithmetic and control circuit to clear any selected and arithmetic counts from the register means and clear the display register, during the fifth step of said higher order section to store a predetermined selected count in the register means, and during the seventh step of said higher order counter section to clear the display register without clearing the selected count from the register;
• and wherein the counter input circuit comprises count indexing logic means for receiving the train of electrical indexing signals, said count indexing logic means connected to said synchronizing circuit means, to said fourth stage of said higher order counter section and to the data entry circuit means and selectively operable by each indexing signal only during the eighth step of said higher order section to selectively apply a timing signal to add to any arithmetic count stored in the register means the predetermined selected count stored in the register means during the reset sequence and store the summation thereof as a new arithmetic count in the register means and display the new arithmetic count with the display register.