High frequency counter having signal level sensitivity

Trigger circuitry comprising:

• trigger means having one input connected to receive a source of bias signal and having another input connected to receive input signal and being operable in one logic state identified by an output of one logic level and in another logic state identified by an output of another logic level, said trigger means being actuated to operate in either one of two logic states in response to input signal applied to said other input with an amplitude greater than a signal level proportional to the amplitude of bias signal applied to said one input;
• bistable means connected to receive the output of said trigger means and operable in one logic state identified by an output of one logic level until reset to another logic state identified by an output of another logic level, said bistable means being actuated to operate in said one logic state in response to an output received from said trigger means, and being actuated to operate in said other logic state in response to a reset signal applied thereto;
• biasing means connected to apply to said one input of the trigger means a bias signal of one level in response to operation of said bistable means in said other logic state, and of another level lower than said one level in response to operation of said bistable means in said one logic state;
• a source of reference signals;
• gate means responsive to the output of the bistable means for passing reference signals therethrough in response to operation of the bistable means in said one logic state;
• logic means coupled to receive the reference signals passed by said gate means for transmitting therethrough the outputs from said trigger means for a selected gate period, and for applying to said bistable means a reset signal after said selected gate period to reset said bistable means to said other logic state;
• and
• counting means connected to said logic means for providing an indication of the accumulated number of pulses transmitted through said logic means during a gate period.