Electronic quartz clock with integrated circuits

In an electronic quartz clock, a frequency divider integrated circuit having an adjustable and programmable dividing factor comprising:

• means for providing a negative voltage;
• a crystal oscillator;
• an asynchronous frequency divider having a predetermined number of stages;
• a blanking circuit coupled between a first predetermined number of divider stages and a second predetermined number of divider stages;
• a switch coupled between said second predetermined number of stages and a third predetermined number of stages such that a portion of said second predetermined number of stages can be cut out of said frequency divider;
• an adjustment circuit for generating a number of control signals, said number being equal to said third predetermined number;
• and
• multiple gate logic means having as inputs said control signals and the outputs of said third predetermined number of stages, said logic means having an output coupled to said blanking circuit for suppressing a number of pulses generated by said oscillator in an evenly distributed manner.