Series logic circuit arrangement using a plurality of complementary IGFET's

In a series logic circuit arrangement using a plurality of P and N channel IGFET's and comprising a plurality of series logic circuits to which a plurality of input binary coded signals are applied, each of said logic circuits being designed to effect a predetermined logic function with respect to any ones of the plurality of input binary coded signals by using at least one P channel IGFET and one N channel IGFET, the improvement in that said P channel IGFET's and N channel IGFET's are arranged according to positive and negative logic systems with respect to the plurality of input binary coded signals, in the negative logic system, said P channel IGFET's being arranged according to a logic equation of minterm-type expression and said N channel IGFET's according to a logic equation of maxterm-type expression, and, in the positive logic system, said P channel IGFET's being provided according to a logic equation of maxterm-type expression and said N channel IGFET's according to a logic equation of minterm-type expression.