Back to results
US 3,944,981 AGranted
Electrical wiring system
AssigneeNippondenso Co., Ltd.
InventorsShigeyuki Akita, Osamu Ito
Life of this patent
Estimating the term…
Abstract
An electrical wiring system in which a plurality of automobile electrical devices and instruction switches for oeprating the electrical devices are interconnected through a single signal line. The transmission of command signals from an instruction unit to the plurality of electrical devices is performed on a time-division multiplex signal transmission basis, and synchronizing high frequency pulse signals and command pulse signals are superposed to form a multiplexed signal so that the signal transmission is accomplished through the single signal line.
Claims6
An electrical wiring system comprising:
- a first circuit including;
- a first oscillator for generating an oscillation pulse signal having a fixed frequency,
- a reference signal generating circuit responsive to said oscillator for dividing the frequency of an output signal of said oscillator and for generating a reference signal, said reference signal having a predetermined period equal to a plurality of cycles of said divided signal and having a group of high frequency pulses at a reference time interval in said predetermined period for effecting timing,
- a first address designating circuit responsive to said reference signal generating circuit for generating a first set of address signals, said first address designating circuit being operable in synchronization with said high frequency pulses in said reference signal and generating said first set of address signals for designating a plurality of addresses by time division of said predetermined period of said reference signal subsequent to the time of synchronization into a plurality of addresses, and
- a transmitter logic circuit connected to said first address designating circuit, said reference signal generator and an instruction unit for generating multiplex signal, said transmitter logic circuit being operable to perform a logic processing of said first set of address signals and a command signal from said instruction unit to produce a series signals containing a series of command pulses separated from each other in respect to time and being operable to produce said multiplex signal by combining said series signal and said reference signal;
- a single signal line connected to said transmitter logic circuit of said first circuit for transmitting said multiplex signal from said transmitter logic circuit;
- and
- a second circuit including;
- a second address designating circuit connected to said single signal line for generating a second set of address signals, said second address designating circuit being operable in synchronization with said high frequency pulses of said reference signal contained in said multiplex signal and generating said second set of address signals for designating addresses respectively by time division of said predetermined period of said reference signal subsequent to the time of synchronization into the same number of addresses as in said first address designating circuit, and
- a receiver logic circuit connected to said single signal line and said second address designating circuit for controlling the actuation of each load corresponding to said command signal through a logic processing of said second set of address signals and said multiplex signal.
7 more elements
An electrical wiring system comprising:
- a first circuit including;
- a first oscillator for generating an oscillation pulse signal having a fixed frequency,
- a reference signal generating circuit responsive to said oscillator for dividing the frequency of an output signal of said oscillator and for generating a reference signal, said reference signal having a predetermined period equal to a plurality of cycles of said divided signal and having a group of high frequency pulses at a reference time interval in said predetermined period for effecting timing,
- a first address designating circuit responsive to said reference signal generating circuit for generating a first set of address signals, said first address designating circuit being operable in synchronization with said high frequency pulses in said reference signal and generating said first set of address signals for designating a plurality of addresses by time division of said predetermined period of said reference signal subsequent to the time of synchronization into a plurality of addresses, and
- a transmitter logic circuit connected to said first address designating circuit, said reference signal generator and an instruction unit for generating multiplex signal, said transmitter logic circuit being operable to perform a logic processing of said first set of address signals and a command signal from said instruction unit to produce a series signals containing a series of command pulses separated from each other in respect to time and being operable to produce said multiplex signal by combining said series signal and said reference signal;
- a single signal line connected to said transmitter logic circuit of said first circuit for transmitting said multiplex signal from said transmitter logic circuit;
- and
- a second circuit including;
- a second oscillator for generating an oscillation pulse signal having the same fixed frequency as said first oscillator,
- a second address designating circuit connected to said second oscillator and said single signal line for generating a second set of address signals, said second address designating circuit being operable in synchronication with said high frequency pulses of said reference signal contained in said multiplex signal and generating said second set of address signals for designating addresses respectively by time division of said predetermined period of said reference signal subsequent to the time of synchronization into the same number of addresses as in said first address designating circuit,
- a first receiver logic circuit connected to said single signal line and said second address designating circuit for controlling the actuation of each load corresponding to said command signal through a logic processing of said second set of address signals of a first region and said multiplex signal;
- and
- a third circuit including;
- a third oscillator for generating an oscillation pulse signal having the same fixed frequency as said first oscillator,
- a third address designating circuit connected to said third oscillator and said single signal line for generating a third set of address signals, said third address designating circuit being operable in synchronization with said high frequency pulses of said reference signal contained in said multiplex signal and generating said third set of address signals for designating addresses by time division subsequent to the time of synchronization into the same number of addresses as in said first address designating circuit, and
- a second receiver logic circuit connected to said single signal line and said third address designating circuit for controlling the actuation of each load corresponding to said command signal through a logic processing of said third set of address signals of a second region and said multiplex signal.
13 more elements
Dependencies are inferred from the claim text.