Digital signal selector device

A special purpose digital signal selector device for receiving a plurality of separate groups of signals, each group including a given number of redundant digital signals, and selecting one of said digital signals from each group for subsequent processing, said device including, in combination:

• a. a plurality of memory sections corresponding in number to said given number of said digital signals, each section having a number of memory locations corresponding to the number of groups, a first memory location in each section being connected to receive and store respectively the redundant digital signals in a first group, a second memory location in each section being connected to receive and store the redundant digital signals in a next group, and so forth so that all of the signals in the plurality of separate groups of signals are stored;
• b. a read only memory means;
• c. address means responsive to said read only memory means connected to said memory sections for successively addressing the memory locations therein;
• d. a number of buffer register means corresponding to said given number of digital signals in each group respectively connected to the output of said address means;
• e. clock means connected to said read only memory means for cycling said address means to transfer the digital signals in the first memory locations of said sections making up the first group of redundant digital signals for storage respectively in successive ones of said buffer register means so that a first buffer register means stores a first digital signal, a second buffer register means stores a second digital signal and so forth until all of the digital signals of said first group are stored;
• f. comparator and selection means connected to said buffer register means for comparing and selecting a preferred one of the digital signals in the first group stored therein, said clock means and read only memory means cycling said address means to transfer the digital signals in the second memory locations of said sections making up the next group of redundant digital signals for storage in said buffer register means, said same comparator and selection means then selecting a preferred one of the digital signals in said next group stored in said buffer register means under control of said clock means;
• and
• g. a high speed memory section connected to the output of said comparator and selection means for storing the selected ones of said digital signals from each group whereby said selected signals are available for subsequent processing.