Error syndrome and correction code forming devices

Abstract

In information handling systems, syndrome and correction codes adapted for error signalling and correcting operations are obtained by processing words each made of a definite number of bytes, each byte having a same number of bits and one of the bytes being comprised of the parity incoming bits of the other bytes. An error syndrome and correction code forming device is described which comprises first and second stages of modulo-2 adders (i.e. exclusive-OR circuits), the number of adders in the second stage being equal to the number of bits in the required code, wherein the adders of the first stage form the parity check bits of the bytes and further bits from selective combinations of bits in the word and wherein the bits outputting the adders of the first stage are distributed, together with further bits of the word, to the inputs of the adders of the second stage. Substantially all the adders of the first stage have at least as many inputs as there are information bytes in the word to be processed and substantially all the outputs of said first stage adders are applied to inputs of at least two adders of the second stage.

Dependencies are inferred from the claim text.