Charge transfer device signal processing
AssigneeTexas Instruments Incorporated
InventorsAl Felix Tasch, Jr., John Millard Caywood
Life of this patent
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Abstract
An input scheme suitable for low-level input signals, e.g., from an IR detector array, wherein the input signals are transferred over respective channels to parallel inputs of a charge transfer device shift register, under control of IGFET switching transistor circuits in each channel. Corresponding IGFETS in the channels are operated by common gate voltages. Introduction of noise due to variation of the gate threshold voltages between IGFETS in the transfer circuits is obviated by using the same IGFET in each channel to reset the potential at the input node of that channel as well as to transfer the input signals over that channel to the shift register.
Claims20
Charge transfer device signal processing apparatus including a charge transfer device shift register having at least one input for receiving analog input signals;
- first semiconductor switch means for connecting said input to a first reference potential during a first clock period;
- second semiconductor switch means including a first transistor switch means for resetting said input to a second predetermined reference potential during a second clock pulse period;
- and third semiconductor switch means operable to connect said input to said charge transfer device shift register during a third clock pulse period for applying an analog input related signal thereto for serial propagation along said shift register said second and third semiconductor switch means each including a common switching transistor means for controlling the resetting of said input to said second predetermined reference potential and for controlling transfer of said input signal from said input into said shift register.
A charge transfer device signal processing system including a charge transfer device shift register, a plurality of inputs for receiving analog input signals, and means for selectively transferring signals from said plurality of inputs in parallel into said shift register at a first clock rate for serial propagation along said shift register at a second clock rate;
- said transfer means including for each input:
- a. first semiconductor switch means operable to connect said input to a first reference potential during a first clock period common to all said inputs;
- and
- b. second semiconductor switch means operable to reset said input to a second predetermined reference potential during a second clock pulse period common to all said inputs;
- and third semiconductor switch means operable to connect said input to said charge transfer device shift register for supplying a parallel input signal thereto during a third clock pulse period common to all said inputs;
- wherein each of said first, second and third semiconductor switch means includes at least one gate controlled majority carrier semiconductor switch device, and wherein said second and third semiconductor switch means include a common gate controlled semiconductor switch device for controlling the resetting of said input to said second referenced potential and for controlling transfer of said input signal from said input into said shift register.
A charge transfer device signal processing system including a charge transfer device shift register, a plurality of inputs for receiving analog input signals, and means including shift register input gating means for selectively transferring signals from said plurality of inputs in parallel into said shift register at a first clock rate for serial propagation along said shift register at a second clock rate,
- said transfer means including for each input:
- a. first and second insulated gate field effect transistors connected in series between said input and a bias potential source;
- b. said first transistor and said input gating means connected in series between said input and a parallel input for said shift register;
- c. a third insulated gate field effect transistor connected between said input and ground;
- said first, second and third transistors and said input gating means including gates connected with respective gate signal lines for applying clock pulses to
- 1. turn on only said third transistor during a first clock period;
- 2. enable only said first and second transistors during a second clock pulse period with a larger gating signal applied to the gate of said second transistor than is applied to the gate of said first transistor;
- and
- 3. enable only said first transistor and said input gating means during a third clock pulse period . with a larger gating signal applied to said input gating means than is applied to the gate of said first transistor.
A charge transfer device signal processing system including a charge transfer device shift register, a plurality of inputs for receiving analog input signals, and means for selectively transferring signals from said plurality of inputs in parallel to input gating means for said shift register at a first clock rate, for serial propagation along said shift register at a second clock rate,
- said transfer means including for each input:
- a. first and second insulated gate field effect transistors connected in series between said input and a bias potential source;
- b. said first transistor connected between said input and said input gating means for said shift register;
- c. a third insulated gate field effect transistor connected between the junction of said first and second transistors and ground;
- said first, second and third transistors and said input gating means including gates connected with respective gate signal lines for applying clock pulses to
- 1. enable only said first and third transistors during a first clock period;
- 2. enable only said first and second transistors during a second clock pulse period with a larger gating signal applied to the gate of said second transistor than is applied to the gate of said first transistor;
- 3. enable only said first transistor and said input gating means during a third clock pulse period with a larger gating signal applied to said input gating means than is applied to the gate of said first transistor.
A charge transfer device signal processing system including a charge transfer device shift register, a plurality of inputs for receiving analog input signals, and means for selectively transferring signals from said plurality of inputs in parallel to input gating means for said shift register at a first clock rate for serial propagation along said shift register at a second clock rate,
- said transfer means including for each input:
- a. first and second insulated gate field effect transistors connected in series between said input and a selectively adjustable bias potential source;
- b. said first insulated gate field effect transistor connected between said input and said input gating means for said shift register;
- said first and second transistors and said input gating means including gates connected with respective gate signal lines for applying pulses to
- 1. enable only said first and second transistors during a first pulse period during which said bias potential source is adjusted to ground potential;
- 2. enable only said first and second transistors during a second pulse period during which said bias potential is adjusted to a predetermined bias level;
- 3. enable only said first transistor and said input gating means during a third pulse period during which said bias potential source is adjusted to said predetermined bias level.
In a charge transfer device signal processing system including a charge transfer device shift register, at least one input for receiving for an analog input signal, and means including charge transfer input gating means for selectively transferring signals from said input for propagation along said shift register;
- said transfer means including:
- a. a first gate controlled transistor connected between capacitor store means and said input gating means for said shift register;
- b. a second gate controlled transistor connected between said input and the gate of said first transistor;
- c. a third gate controlled transistor connected between a bias potential source and the gate of said first transistor;
- and
- d. a fourth gate controlled transistor connected between a selectively adjustable bias source and said input gating means for said shift register;
- said third and fourth transistors and said input gating means having gates connected with respective gate signal lines for applying clock pulses:
- 1. to enable only said third and fourth transistors during a first clock period initially with said adjustable bias supply at a first predetermined value to permit discharge of said capacitor store means through said first transistor, and then with said adjustable bias supply at a second predetermined value to charge said capacitor store means through said first transistor to a reference potential determined by the gate voltage of said first transistor;
- 2. to enable only said input gating means and said third transistor during a second clock pulse period;
- 3. to enable only said input gating means during application of a signal input to the gate of said second transistor to apply said signal input as a gate voltage to said first transistor to cause discharge of said capacitor store means through said first transistor and said input gating means to enter into said shift register an amount of charge determined by the input signal dependent gate voltage of said first transistor.
Dependencies are inferred from the claim text.