Memory diagnostic arrangement

For use in a memory system having a memory module for storing information, which information must be periodically refreshed within a predetermined time interval to maintain the viability of the information, and means for providing a refresh signal indicating that a refresh operation is to be commenced and for providing an address identifying a group of locations in said module containing information which is to be refreshed, a diagnostic arrangement comprising

• first access means responsive to said refresh signal and to said address for applying control signals to said module to control said module to restore the information stored in certain of said identified group of locations,
• second access means responsive to said refresh signal and to said address for applying control signals to said module to control said module to restore the information stored in the remaining of said identified group of locations,
• means connected to said access means for comparing the control signals provided by said first access means with the control signals provided by said second access means, and
• means responsive to said comparing means for generating an error indication if said control signals mismatch.

For use in a memory system wherein a memory module storing a plurlity of words comprises a plurality of memory planes including decoder circuits, each of said memory planes storing a predetermined number of bits of each of said words, a diagnostic arrangement comprising

• means for providing address information identifying a word,
• first buffer means connected to certain of said memory planes and responsive to said address information for providing control signals to said certain memory planes to control each of said certain memory planes to access said predetermined number of bits of said identified word stored therein,
• second buffer means connected to the remaining ones of said memory planes and responsive to said address information for providing control signals to said remaining planes to control each of said remaining planes to access said predetermined number of bits of said identified word stored therein, and
• means for comparing said control signals provided by said first buffer means with said control signals provided by said second buffer means, and for providing an error signal if said control signals mismatch.

A diagnostic arrangement for ascertaining whether a memory is being properly accessed comprising

• control means for providing control information including an address identifying one of the words stored in said memory,
• first access means responsive to said control information for generating and then applying a first set of signals to said memory to access predetermined bits of said one word,
• second access means concurrently responsive to said control information for generating and applying a second set of signals to said memory to access the remaining bits of said word,
• first parity generating means for computing parity over said first set of signals.
• second parity generating means for computing parity over said second set of signals, and
• means for comparing said parities computed by first and second parity generating means and for providing an error signal if a mismatch is detected.

A diagnostic arrangement for ascertaining whether a memory comprising a plurality of volatile storage elements is being properly accessed for refreshing the information stored in said storage elements, which comprises

• control means for providing control information including an address identifying a group of said storage elements which are to be refreshed,
• first access means responsive to said control information for generating and applying a first set of signals to said memory to refresh the information stored in predetermined ones of said storage elements in said group,
• second access means concurrently responsive to said control information for generating and applying a second set of signals to said memory to refresh the information stored in the remaining ones of said storage elements in said group,
• first parity generating means for computing parity over said first set of signals,
• second parity generating means for computing parity over said second set of signals, and
• means for comparing said parities computed by said first and second parity generating means and for generating a mismatch signal when said parities do not match.