US 3,943,551 AGranted

LSI array using field effect transistors of different conductivity type

AssigneeRCA Corporation

InventorGordon Edward Skorup

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Abstract

A large scale integrated (LSI) array of standard cells arranged in rows and columns adapted to receive different metallization patterns for producing custom circuits. Disposed in one half of each cell is a first power contact and contacts for the sources, drains and gates of field effect transistors of one conductivity type. Disposed in the other half of each cell is a second power contact and contacts for the sources, drains and gates of field effect transistors of complementary conductivity type. The pattern formed by the contacts in one half of a cell is the mirror image of the pattern formed by the contacts in the other half of the cell. The symmetry of the components of each cell is such that the metal interconnection pattern of a cell or a combination of cells for producing a given logic function may be inverted about the horizontal or the vertical plane of symmetry of the cell for producing a logic function relates to said given logic function.

Claims13

Dependent claims

A cell having a surface on which are formed contacts adapted to receive different interconnection patterns for producing different functions, said cell comprising:

a first plurality of transistors of first conductivity type, and a second plurality of transistors of second conductivity type;
each one of said transistors having first and second regions defining the ends of a conduction path and a control electrode for controlling the conductivity of the conduction path;
the first and second regions of the transistors of said first conductivity type being physically located to have their conduction paths lying end-to-end, and the first and second regions of the transistors of said second conductivity type being physically located to have their conduction paths lying end-to-end;
a first set of said contacts, connected to the first and second regions of said first plurality of transistors;
a second set of said contacts connected to the first and second regions of said second plurality of transistors;
the first and second regions of each transistor being connected to different contacts, with adjacent transistors of the same conductivity type having a common region connected to a contact;
two additional contacts, one being designated as a first power contact and the other being designated as a second power contact for the application therebetween of an operating potential for the cell, said first and second power contacts being associated with and disposed adjacent to and apart from said first and second sets of contacts, respectively;
and
said first power contact and the contacts for said first plurality of transistors forming a pattern which is the mirror image of the pattern formed by said second power contact and the contacts for said second plurality of transistors with respect to a plane of symmetry lying between said first and second plurality of transistors.

6 more elements

A cell having conductive contacts adapted to receive different interconnection patterns for producing different functions, comprising:

a body of material having a surface;
a first plurality of transistors of first conductivity type, each having two spaced apart doped regions of said first conductivity type, disposed along said surface, defining the ends of the conduction path of a transistor and a control electrode overlying the space between said two regions;
a second plurality of transistors of second conductivity type, each including two spaced apart doped regions of second conductivity type, disposed along said surface, defining the ends of the conduction path of a transistor and a control electrode overlying the space between said two doped regions;
a first set of said conductive contacts disposed along said surface for contacting said spaced apart regions of said first plurality of transistors, and a like set of said conductive contacts disposed along said surface for contacting said spaced apart regions of said second plurality of transistors;
two additional ones of said conductive contacts designated as first and second power contacts;
said first and second power contacts being spaced apart and disposed along said surface of said body for the application therebetween of an opeating potential for said cell, said first power contact being located adjacent to and apart from said first plurality of transistors, and said second power contact being located adjacent to and apart from said second plurality of transistors;
and
said first power contact and the contacts for said first plurality of transistors being arranged to form a pattern which is the mirror image of the pattern formed by said second power contact and the contacts for said second plurality of transistors with respect to a plane of symmetry lying between said first and second plurality of transistors.

5 more elements

Dependencies are inferred from the claim text.