High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same
AssigneeInternational Business Machines Corporation
InventorsIrving T. Ho, Jacob Riseman
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Abstract
An improved FET structure and method of making same is disclosed. The gate structure of the FET includes a phospho-silicate glass as the insulator and polysilicon as the gate conductor. A thin layer of silicon nitride is formed over the polysilicon and selectively etched so as to remain only over gate areas and other areas where it is desired to extend the polysilicon as a conductor. The unmasked polysilicon is oxidized to form the thick oxide surface coating. The disclosure also describes the use of oxide rings and epitaxial layers to reduce parasitic effects between adjacent FET devices in an integrated circuit.
Claims7
A field effect transistor comprising:
- a. a layer of monocrystalline silicon of a first type conductivity,
- b. diffused drain and source regions of a second type conductivity, opposite said first type, said diffused drain and source regions formed in the surface of said monocrystalline silicon layer and separated from one another by a portion of said layer of first type conductivity, and
- c. a gate structure covering said portion, said gate structure comprising a thin oxide insulating layer in contact with said surface between said drain and source diffusions, a conductive polysilicon gate electrode covering said thin oxide insulating layer, and a layer of silicon nitride covering said polysilicon which overlies said portion.
Dependencies are inferred from the claim text.