Memory clocking system
AssigneeRockwell International Corporation
InventorsClarence W. Padgett, Francis L. Newman
Life of this patent
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Abstract
A solid state memory employs a plurality of memory cells each capable of storing either of two different binary values. The memory cells require periodic application of a refresh pulse to the memory cell to, without rewriting, enhance at least one of the two different binary values which the memory cells can store, in order to prevent loss of that binary value over a period of time. The reliability of the memory is improved by supplying a refresh signal which includes a plurality of refresh pulses in each memory cycle.
Claims14
Refresh clock signal generating means for generating a refresh clock signal from first and second clock signals, said refresh clock signal including a plurality of pulses per clock cycle, said generating means comprising:
- clocked time delay means having an input terminal and an output terminal, said input terminal connected to a source of said first clock signal for initiating a delay period when said first clock signal obtains a predetermined state;
- first ratio means having first and second input terminals and an output terminal, said first input terminal connected to the output terminal of said clocked time delay means, said second input terminal connected to the source of said first clock signal;
- second ratio means having first and second input terminals and an output terminal, said first input terminal thereof connected to the output terminal of said first ratio means, and said second input terminal thereof connected to the source of said first clock signal;
- first inverter means having an input and an output terminal, said input terminal thereof connected to the output terminal of said second ratio means;
- gate means having first, second and third input terminals, said first input thereof connected to the output terminal of said second ratio means, said second input terminal thereof connected to the output terminal of said first inverter means and said third input terminal thereof connected to a source of said second clock signal;
- and
- second inverter means having an input and an output terminal, said input terminal thereof connected to the output terminal of said gate means, and the signal at the output terminal thereof comprising the output signal of the refresh clock signal generator.
In an electronic memory system of a plurality of memory cells each capable of storing either of two different binary values, each memory cell requiring a periodic application of a refresh pulse to the memory cell to, without rewriting the information contained therein, enhance at least one of said two different binary values in order to prevent the loss of said at least one binary value over a period of time and in which each memory access cycle has a first predetermined portion which is dedicated as a read period and a second predetermined portion which is dedicated as a write period, the method of operating the memory comprising the step of applying to said memory cells during each said memory cycle a refresh signal which includes a plurality of refresh pulses within said memory cycle.
In an electronic memory system of a plurality of memory cells each capable of storing either of two different binary values, each memory cell requiring a periodic application of a refresh pulse to the memory cell to, without rewriting the information contained therein, enhance at least one of said two different binary values in order to prevent the loss of said at least one binary value over a period of time and in which each memory access cycle during which information is to be written into said memory includes a write period, the method of operating the memory comprising the step of applying to said memory cells during each said memory cycle a refresh signal which includes a plurality of refresh pulses each of which, during said write period refreshes the information stored in said memory cells.
An electronic memory system comprising:
- a plurality of memory cells each capable of storing either of two different binary values, each of said memory cells requiring the periodic application of a refresh pulse to the memory cell to, without rewriting the information contained therein, enhance at least one of said two different binary values in order to prevent the loss of said at least one binary value over a period of time;
- and
- means for applying to said memory cells during each memory cycle a refresh signal including a plurality of refresh pulses within said memory cycle.
Dependencies are inferred from the claim text.