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US 3,943,494 AGranted
Distributed execution processor
AssigneeInternational Business Machines Corporation
InventorsArthur Wilbert Holmes, Jr., Price Ward Oman, Richard Charles Paddock, Donald Walter Price
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Abstract
A processor including a plurality of synchronized subprocessors, each implemented on an integrated circuit substrate and each having an instruction register and instruction executing circuits for independently executing a portion of the functions required by an instruction being simultaneously executed by each subprocessor. Execution is initiated and synchronized by simultaneously loading the same instruction into each subprocessor.
Claims8
A data processing system comprising:
- a memory for storing instruction information and data information, said memory having an information output, an information input, and an address input;
- a first subprocessor having a first information input and an address output, said first information input being connected to said information output of said memory, said address output being connected to said address input of said memory;
- said first subprocessor having an OP register for storing the operation code portion of an instruction, an input to said OP register being connected to said first information input;
- said first subprocessor further having first instruction decoding means connected to outputs from said OP register for decoding an instruction received from said memory means, said first decoding means having a function modifier input for receiving a signal for modifying the function specified by said instruction;
- a second subprocessor time synchronized to said first subprocessor, said second subprocessor having a second information input and an information output, said second information input being connected to said information output of said memory, said information output of said second subprocessor being connected to said information input of said memory;
- said second subprocessor having a second OP register for storing the operation code portion of an instruction, an input to said second OP register being connected to said second information input;
- second instruction decoding means connected to said second OP register for decoding said instruction;
- an operand register having a load input connected to outputs of said second instruction decoding means for loading said operand register from said second information input when an operand is to be stored therein;
- arithmetic and logic decision circuits having a plurality of inputs connected to outputs of said second instruction decoding means for performing arithmetic and logic decisions upon data received from an input connected to said operand register and information received from an input connected to said second information input of said second subprocessor, an output of said arithmetic and logic decision circuitry being connected to said information output of said second subprocessor;
- and function modifying logic having inputs connected to said arithmetic and logic decision circuits, responsive to data information from said memory, an output from said function modifying logic being connected to said function modifier input of said first decoding means;
- whereby each of said subprocessors is functionally responsive in a different predetermined manner to said instruction to perform a data processing operation as specified by said instruction upon information from said memory.
8 more elements
Dependencies are inferred from the claim text.