Time switch circuit having a switch-back time delay
AssigneeITT Industries, Inc.
InventorGerhard Achtstaetter
Life of this patent
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Abstract
This relates to a circuit for use in a car interlock and permits restarting of the motor for about three minutes after the unfastening of the safety belt. The circuit contains a difference amplifier, a first input switching the supply voltage of a capacitor charging circuit and a second input directly switching the charging circuit.
Claims7
A circuit having a delayed starting storage behavior in response to a first input signal and having a substantially longer delayed stoppage of said storage behavior in response to a second input signal, comprising:
- means for receiving a supply voltage;
- an RC parallel circuit having one end coupled to the zero point of the circuit;
- a first diode;
- a first current mirror circuit having first and second current outputs, said first output coupled to said first diode for charging said RC-circuit;
- a second diode;
- a first transistor having a base for receiving said second input signal, an emitter coupled to the zero point of the circuit via said second diode, and a collector coupled to said first current mirror circuit for switching on and off said second current output;
- a source of a fixed predetermined voltage;
- a differential amplifier having a first input coupled to said RC-circuit and a second input coupled to said source;
- a second current mirror circuit coupled between the zero point of the circuit and said differential amplifier;
- a third current mirror circuit coupled between said means for receiving and said differential amplifier;
- a second transistor having a base coupled to said second current mirror circuit and to said differential amplifier, a collector coupled to the collector of said first transistor, and an emitter for serving as a first output;
- a third transistor having an emitter coupled to the zero point of the circuit, a collector coupled to said means for receiving, and a base for receiving said first input signal;
- and
- a fourth transistor having an emitter coupled to said means for receiving, a base coupled to the collector of said third transistor and a collector coupled to said first current mirror circuit.
A circuit having a delayed starting storage behavior in response to a first input signal and having a substantially longer delayed stoppage of said storage behavior in response to a second input signal, comprising:
- means for receiving a supply voltage;
- an RC parallel circuit having one end coupled to the zero point of the circuit;
- a first diode;
- a first current mirror circuit having first and second current outputs, said first output coupled to said first diode for charging said RC-circuit;
- a first transistor having a base for receiving said second input signal, and a collector coupled to said first current mirror circuit for switching on and off said second current output;
- a source of a fixed predetermined voltage;
- a differential amplifier having a first input coupled to said RC circuit and a second input coupled to said source;
- a second current mirror circuit coupled between the zero point of the circuit and said differential amplifier;
- a third current mirror circuit coupled between said means for receiving and said differential amplifier;
- a second transistor having a base coupled to said second current mirror circuit and to said differential amplifier, a collector coupled to the collector of said first transistor, and an emitter for serving as a first output and coupled to the emitter of said first transistor;
- a third transistor having an emitter coupled to the zero point of the circuit, a collector coupled to said means for receiving and a base for receiving said first input signal;
- and
- a fourth transistor having an emitter coupled to said source of supply voltage, a base coupled to the collector of said third transistor and a collector coupled to said first current mirror circuit.
Dependencies are inferred from the claim text.