Data processor reorder random access memory

In a system for coupling output signals from a first processor to the input means of a second processor wherein the input signals to said second processor are represented by a different schema from the schema of the output signals from said first processor, the improvement comprisng:

• first memory means for storing the output signals from said first processor, said first memory means having data input means, data output means, and addressing means;
• second memory means for storing signals specifying a first group of first memory addresses corresponding to the schema of input signals to said second processor, said second memory having addressing means and output means;
• timing signal means for producing a pluraity of signals in time sequence representing successive binary numbers;
• means for coupling said timing signals to the addressing means of said first memory means as a first address;
• means for coupling a subset of said timing signals to the addressing means of said second memory means;
• first adder means responsive to said output means of said second memory and to said timing signals for producing sum output signals;
• means for coupling said sum output signals from said first adder means to the addressing means of said first memory means as a second address;
• means responsive to said timing signals for storing data in said first memory means at one of said addresses and for retrieving data from said first memory means at the other of said addresses;
• means for coupling the output signals from said first processor to the data input means of said first memory means;
• and
• means for coupling the data output means from said first memory means to the input means of said second processor.