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US 3,942,173 AGranted
Offset error compensation for integrating analog-to-digital converter
AssigneeAnalog Devices, Inc.
InventorIvar Wold
Life of this patent
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AssigneeAnalog Devices, Inc.
InventorIvar Wold
Estimating the term…
An analog-to-digital converter of the ramp-integrator type utilizing a special technique to reduce errors due to offset voltages. In a pre-conversion cycle, the integrator first is ramped away from a datum level and then back to that level, by sequential application of opposite-polarity reference signals. A digital net offset error is thereby determined as the difference in clock time between (a) the total time of ramp-up-and-back and (b) a fixed time period set by a clock generator. During the subsequent conversion cycle, the integrator is ramped up by the unknown analog signal and then is ramped back by a reference signal. The time of ramp-up is controlled in accordance with the amount of previously-determined net offset error so as to provide error correction. In the embodiment disclosed, the ramp-up time during the pre-conversion cycle is set at k/2 clock pulses, and the digital offset error is the difference in clock pulse time between the return to datum level and a fixed time of k clock pulses. The ramp-up time during the conversion cycle is terminated at 2k clock pulses following start of the pre-conversion cycle, so that the integration time is set at k-n clock pulses where n is the digital error in clock pulses determined in the pre-conversion cycle. The digital output signal is defined as the number of clock pulses between the final return to datum level and the time of 2k of clock pulses following the start of the conversion cycle.
In an analog-to-digital converter having an integrator which is first operated under control of reference signal means through a pre-conversion cycle wherein the integrator is ramped away from a datum level for a predetermined clock-pulse time and then is ramped back to the datum level, whereby the difference between the clock-pulse time of return to said datum level and a first predetermined clock-pulse time after the start of said pre-conversion cycle defines a digital offset error signal;
In an analog-to-digital converter of the type comprising an integrator arranged to produce a linear ramp signal at a ramp rate corresponding to an applied input signal;
In an analog-to-digital converter of the type comprising an integrator arranged to produce a linear ramp signal at a ramp rate corresponding to an applied input signal, and wherein the integrator first is operated through a pre-conversion cycle in which it is ramped by reference signal means away from a datum level for a predetermined first clock-pulse time period and then is ramped back to the datum level to produce a digital indication of offset error;
Dependencies are inferred from the claim text.