Sense line coupling reduction system
AssigneeSemi, Inc.
InventorWilliam C. Dunn
Life of this patent
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Abstract
The inductive and capacitive coupling between adjacent sense lines in a semi-conductor memory is minimized by periodically interchanging the locations of the two sense lines assigned to each column of storage cells in a semi-conductor memory.
Claims4
In a semi-conductor memory wherein the storage elements of said memory are arranged in an array of rows and columns and there is provided a parallel pair of sense lines for each column of memory elements, to which all the elements of a column are connected, the improvement comprising,
- transposing the locations of the sense lines in each pair of sense lines which are alternate pairs of sense lines in said array at a first predetermined distance from one end along the length of said alternate pairs of sense lines, and
- interchanging the locations of each pair of sense lines in the remaining pairs of sense lines at a second predetermined distance from one end of each said pair of remaining pairs of sense lines.
In a semi-conductor memory of the type wherein a plurality of storage cells of the binary storage type are disposed in an array of columns and rows over the over the surface of a chip, and there is provided a pair of sense lines for each column of storage cells to which all of the storage cells in a column are connected, said sense lines in each column extending parallel to one another on said chip, the method of reducing coupling effects comprising,
- interchanging the locations of the sense lines associated with alternate columns of memory cells at a first predetermined location along the length thereof, and
- interchanging the location of the sense lines in each pair of sense lines in the remaining alternate columns at a second predetermined location for reducing the electrical coupling between sense lines in adjacent columns.
Dependencies are inferred from the claim text.