US 3,942,163 A · CCD stack memory organization

Abstract

A stack memory having a last-in-first-out memory organization comprising a plurality of pairs of two-phase charge coupled device shift registers arranged into a plurality of rows, the CCD registers of each pair being interconnected by digital logic to provide a circular shift register cell and to direct data into and out of the cell. Each cell is interconnected through its logic to an adjacent cell within the same row, and each row of a plurality of circular shift register cells is interconnected between an input buffer register and an output buffer register. The input buffer register is used to write data into each one of the plurality of rows of cells, and the output buffer register is used to retrieve the data from each row of cells. A system control is included for controlling the read, write, and idle operations, wherein a CCD circular shift register cell provides a control loop for maintaining synchronization over the memory system, and wherein there is also provided a clock generator and switch means for generating clock signals.

Claims10

Dependent claims

A charge coupled device stack memory system providing last-in-first-out operation in response to read and write signals comprising:

an input buffer means for storing data to be inputted to said stack;
an output buffer means for storing data to be outputted from said stack;
a plurality of rows each including a plurality of loops of charge coupled shift register cells;
means for applying a two phase clock to circulate the data bits in said cells;
first logic means for gating data from said input buffer means to the first loop in each said row and from each loop in a said row to the next successive loop in that row in response to a first control signal, for gating data to the said output buffer means from each said first loop and from each loop in a said row to the next preceding loop in that row in response to a second control signal and for gating data around said loop in response to third and fourth control signals;
control means for maintaining an indication of the position of the data bits in said shift register cells;
and
second logic means responsive to a said read signal, a said write signal and said indication of said control means to produce said first, second, third and fourth control signals.

5 more elements

The CCD stack memory system of claim 7, wherein each of said loops has a data feed input, a data feed output, a data return input and a data return output and the data feed input of the leftmost register of each one of the said rows of two-phase CCD shift registers in connected to an individual output of said input buffer register;

the data feed output of each register being connected to the data feed input of the adjacent register to the right for transmitting data bits between said registers, proceeding from left to right in any one row of said registers;
the data return output of each register being connected to the data return input of the adjacent register to the left for transmitting data bits between said registers, proceeding from right to left in any one row of said registers;
and the data return output of the leftmost register of each one of said rows of registers being connected to an individual input of said output buffer.

Dependencies are inferred from the claim text.

CCD stack memory organization

Life of this patent

CCD stack memory organization

Life of this patent

Abstract

Claims10