Bit sense line speed-up circuit for MOS RAM

Abstract

A speed-up circuit for a bit sense line of an MOS RAM includes a cross-coupled latch circuit having an output coupled to the bit sense line. When partial discharging of the bit sense line is accomplished through the selected storage cell, the latch circuit switches states and completes discharge of the bit sense line much more rapidly than could have been achieved by the action of the selected storage cell alone. A disabling circuit is connected to the gate of a pull-down MOSFET of the latch circuit connected to the output thereof to turn off the pull-down MOSFET during a write cycle or during the write portion of a read-modify-write cycle. The output of the disabling, or turn-off, circuit operates in response to a signal derived from a clock signal and a chip enable signal applied to the MOS RAM. A bootstrap circuit is provided including a bootstrap charging MOSFET having its gate coupled to V.sub.DD, its source coupled to the bootstrap capacitor, and its drain coupled to a clock signal conductor, to provide low-power dissipation and fast rise time.

Dependencies are inferred from the claim text.