Digital repetition rate check circuit

Abstract

A pulse repetition rate check circuit of the type which detects when the second of two consecutive pulses from a pulse generator is early or late with respect to a predetermined repetition time period includes an early pulse detector, first and second early pulse detector enabling means and first and second clocks. Each early pulse detector enabling means enables the early pulse detector responsive to its associated clock for a predetermined time so that a second pulse occurring within the predetermined time is detected as an early second pulse. The early pulse detector enabling means includes an inhibit means for preventing the enabling of the early pulse detector after it has been once enabled. A steering circuit alternately directs the clocking signals from an oscillator to the clocks responsive to alternate pulses and a clock reset means associated with each clock causes each clock to be reset responsive to the other clock to assure that one clock is always conditioned to act upon the receipt of the next pulse. The pulse repetition rate check circuit also includes first and second late pulse detectors which are coupled to the first and second clocks respectively for providing an error signal indicating that the second pulse is late should the second pulse fail to occur within the predetermined repetition time period.

Dependencies are inferred from the claim text.