MOS edge sensing circuit
AssigneeMotorola, Inc.
InventorWilliam David Mensch, Jr.
Life of this patent
Estimating the term…
Abstract
An edge sensing circuit is implemented using MOS logic gates. The edge sense circuit detects either a positive transition or a negative transition of a first input signal, depending on the logic level of a second input signal, if an enable signal logical "1" is applied to the edge sense circuit. If the enable signal is at a logical "0," however, a level, rather than a transition, of the input signal is detected.
Claims10
A transition sensing circuit coupled to an input conductor, an enable signal conductor, and a first control conductor and including first and second nodes, said transition sensing circuit comprising:
- gating circuit means coupled to said input conductor, said control conductor and said first and second nodes for providing a high logic level at one of said first or second nodes indicative of a positive signal transition at said input conductor conditional upon said first control conductor being at a first logic level, or providing a high level at the other of said first or second nodes indicative of a negative transition at said input conductor conditional upon said first control conductor being at a second logical level;
- flip-flop circuit means coupled to said enable conductor and to said first and second nodes of said gating circuit means responsive to signals at said first and second nodes for switching to a stored state indicative of sensing of a positive or a negative transition, said flip-flop circuit means having first and second outputs thereof;
- and
- output circuit means having an output and being coupled to said first and second outputs of said flip-flop circuit means for generating a signal at said output indicative of sensing of a transition of a signal at said input conductor.
A transition sensing circuit connected to an input conductor, an enable conductor, a first control conductor, and a second control conductor comprising:
- a first inverter having an input connected to said input conductor and an output connected to a first node;
- a second inverter having an input connected to said first control conductor and an output connected to a second node;
- a first NOR gate having an input connected to said second control conductor, another input connected to said second node, and an output connected to a third node;
- a second NOR gate having an input connected to said second control conductor, and another input connected to said first control conductor and an output connected to a fourth node;
- a third NOR gate having an input connected to said first node, another input connected to said third node, and an output connected to a fifth node;
- a fourth NOR gate having an input connected to said fourth node, and another input connected to said input conductor and an output connected to a sixth node;
- and AND gate having an input connected to said enable conductor and another input connected to said fifth node;
- a second AND gate having an input connected to said enable conductor and another input connected to said sixth node;
- a fifth NOR gate having an input connected to an output of said first AND gate and another input connected to a seventh node and an output connected to an eighth node;
- a sixth NOR gate having an input connected to said eighth node and another input connected to an output of said second AND gate and an output connected to said seventh node;
- a third AND gate having an input connected to said first control conductor, another input connected to said eighth node, an another input connected to said input conductor;
- a fourth AND gate having an input connected to said seventh node, another input connected to said first node, and another input connected to said second node;
- and
- a seventh NOR gate having one input connected to an output of said third AND gate another input connected to an output of said fourth AND gate and an output connected to a ninth node.
Dependencies are inferred from the claim text.