Current mode logic circuit

A non-saturating logic circuit comprising:

• a. an M number of current mode input gates, each current mode input gate including a group of common collector node input logic switching transistors, and an interconnected reference voltage switching transistor;
• b. a first node logic connection, the reference voltage switching transistor associated with each of the M input gates being collector dotted to the first node logic connection;
• c. a current mode output gate, the output gate including an input switching transistor coupled to the first node logic connection and M interconnected selectively enabled reference transistors;
• d. a first load diode coupled to a reference voltage source means and to the first node logic connection for establishing a logic level signal swing at the input switching transistor of the output gate in response to the application of input logic signals to the input gates;
• e. each of the M reference transistors of the output gate being coupled, respectively, to one of the group of common collector node input logic switching transistors so as to be selectively enabled;
• and
• f. the output gate being responsive to a logic level signal swing at the first node logic connection and to the selective enabling of the M reference transistors for generating an output logic level signal.