US 3,942,014 A · Logic elements for reactor period meter

Abstract

Logic elements are provided for a reactor period meter trip circuit. For one element, first and second inputs are applied to first and second chopper comparators, respectively. The output of each comparator is O if the input applied to it is greater than or equal to a trip level associated with each input and each output is a square wave of frequency f if the input applied to it is less than the associated trip level. The outputs of the comparators are algebraically summed and applied to a bandpass filter tuned to f. For another element, the output of each comparator is applied to a bandpass filter which is tuned to f to give a sine wave of frequency f. The outputs of the filters are multiplied by an analog multiplier whose output is 0 if either input is 0 and a sine wave of frequency 2f if both inputs are a frequency f.

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Drawings

Claims9

Dependent claims

A logical device for indicating the condition of the value of a first input signal being equal to or greater than a first trip level and simultaneously the value of a second input signal being equal to or greater than a second trip level, comprising:

first DC means for developing a first DC signal corresponding to the first trip level, a first chopper comparator having the first input signal applied thereto and being coupled to said first DC means, said first comparator being responsive to the first input signal and said first DC signal to develop a first comparator signal, with the first input signal less than said first DC signal said first comparator signal being a square wave of frequency f and with the first input signal equal to or greater than said first DC signal said first comparator signal having 0 value,
second DC means for developing a second DC signal corresponding to the second trip level, a second chopper comparator having the second input signal applied thereto and being coupled to said second DC means, said second comparator being responsive to the second input signal and said second DC signal to develop a second comparator signal, with the second input signal less than said second DC signal said second comparator signal being a square wave of frequency f and with the second input signal equal to or greater than said second DC signal said second comparator signal having 0 value, and
a first bandpass filter tuned to frequency f and being coupled to said first and second comparators and being responsive to said first and second comparator signals to develop a first AC alarm signal of frequency f with either of said comparator signals of frequency f and having zero value with both said comparator signals not of frequency f.

A logical device for indicating the condition of the value of either of two input signals being in excess of respective trip levels, comprising:

first DC means for developing a first DC signal corresponding to said first trip level, a first chopper comparator having applied thereto said first DC signal and being coupled to said first DC means, said first comparator being responsive to said first input signal and said first DC signal to develop a first comparator signal, with said first input signal less than said first DC signal said first comparator signal being a square wave of frequency 1/2 f and with said first input signal equal to or greater than said first DC signal said first comparator signal having zero value, second DC means for developing a second DC signal corresponding to said second trip level, a second chopper comparator having applied thereto said second DC signal and being coupled to said second DC means, said second comparator being responsive to said second input signal and said second DC signal to develop a second comparator signal, with said second input signal less than said second DC signal said second comparator signal being a square wave of frequency 1/2 f and with said second input signal equal to or greater than said second DC signal said second comparator signal having zero value, a first bandpass filter tuned to frequency 1/2 f coupled to said first comparator and being responsive to the comparator signal thereof to develop a first AC alarm signal of frequency 1/2 f with the comparator signal applied thereto of frequency 1/2 f and of zero value with the comparator signal applied thereto not of frequency 1/2 f, a second bandpass filter tuned to frequency 1/2 f coupled to said second comparator and being responsive to the comparator signal thereof to develop a second AC alarm signal of frequency 1/2 f with the comparator signal applied thereto of frequency 1/2 f and of zero value with the comparator signal applied thereto not of frequency 1/2 f, and an analog frequency multiplier coupled to said first and second bandpass filters and being responsive to said first and second AC alarm signals to develop an AC scram signal, with either of said first and second AC alarm signals having zero value said AC scram signal having zero value and with both said first and second AC alarm signals of frequency 1/2 f said AC scram signal having a frequency of f.

Dependencies are inferred from the claim text.

Description2,556 words

Summary504 words

#A reactor period meter is a device for monitoring a reactor's period T. With the reactor period below a critical value, that is, it is too short, the power level is increasing too quickly. A reactor scram signal should be initiated by the reactor period meter, indicating the reactor power should be reduced. Such a meter includes means for developing a signal proportional to reactor period and logical elements for determining whether the reactor period indicated by the signal is at a critical scram level. For use in a reactor period meter, such logic elements should be fail safe, and should indicate scram condition with the reactor period at the scram level and it should indicate scram condition with failure of any of the components of the period meter. With D.C. digital, logical elements, failure of the logic elements themselves might not necessarily cause a scram signal to be generated by the meter. Thus, constant checking of the meter in a nonoperational condition is required.

#It is therefore an object of this invention to provide fail safe logic elements.

#Another object of this invention is to provide fail safe logic elements for a reactor period meter.

Brief description of the drawings15 words

#The drawing is a block diagram showing logic elements of an improved reactor period meter.

Detailed description2,037 words

#Referring to the drawing, there is shown a reactor period meter with fail safe logic elements. The reactor period meter shown in the drawing is a log N-type meter having an ionization chamber 10 which develops a signal proportional to the neutron flux density for power level of the reactor (not shown). The neutron flux density is proportional to reactor power level. The output of the chamber 10 is applied to log N amplifier 12. The output of log N amplifier 12 is proportional to the log of the reactor power level. The type of meter shown in the drawing has two circuits for determining reactor period. One circuit is limited to high power levels, while the other functions at all reactor power levels. This is more particularly described in U.S. Pat. application Ser. No. 509,971(70) filed Sept. 27, 1974. The present application relates to particular fail safe logic elements incorporated into such a reactor period meter.

#The output V of log N amplifier 12 is applied to differentiator 14 whose output is proportional to dV/dt. The output of differentiator 14 is applied to a fail safe logical element 16 which determines whether dV/dt is greater than a particular critical value and simultaneously whether V is greater than a predetermined number. The dV/dt comparison tests the critical reactor period while the V comparison tests the reactor power level. Logic element 16 is designed so that at high power levels dV/dt is used to monitor reactor period.

#The dV/dt signal is applied to chopper comparator 18. A chopper comparator is a device which chops a resulting D.C. signal determined by subtracting from a reference D.C. an applied signal. Only if the subtraction is positive will the resulting D.C. signal be chopped. However, if the subtraction is negative or 0, the output of chopper comparator 18 will be 0. Chopping means that the comparator generates a square wave in response and proportional to the amplitude of the positive resulting D.C. signal. The frequency of the square wave will be equal to that of a reference A.C. signal applied to the chopper comparator. In the drawing, the chopper comparator 18 compares the value of the applied input signal dV/dt signal with a particular D.C. scram level established by scram setting 20. If dV/dt is greater than the D.C. scram level, comparator 18 will chop the positive resulting D.C. signal. The chopped square wave will have a frequency equal to the frequency of an A.C. reference signal, which in this embodiment is a 1 KHz signal developed by A.C. source 22. The actual reference A.C. signal is chosen for convenience. If the D.C. scram level is not exceeded by the dV/dt signal, the output of comparator 18 is 0. Simultaneously, the output of log N amplifier 12 is applied to chopper comparator 24 which compares the value of V with a D.C. power level established by power setting 26. If V is equal to or exceeds the D.C. power level, comparator 24 develops a 0 output. If the V signal is greater than the D.C. power level, then the output of chopper comparator 24 is a square wave of frequency equal to the reference A.C. signal applied to comparator 24 by A.C. source 22. In logic element 16 this frequency is the same as that applied to comparator 18, which in this embodiment is 1 KHz.

Facts

Application

05/560,429Filed 20 Mar 1975

Granted

2 Mar 1976

Term ended

2 Mar 1993

Estimated · how

Pre-1995 term; greater of 17 years from grant or 20 years from filing when eligible. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification4 codes

G21C 17/14
Monitoring; Testing ; Maintaining: period meters
Y02E 30/30
Energy generation of nuclear origin: nuclear fission reactors
G21C
Nuclear reactors
Y02E
Clean energy generation and storage

Logic elements for reactor period meter

Life of this patent

Logic elements for reactor period meter

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims9

Description2,556 words

Drawings

Classification4 codes

Life of this patent

Description2,556 words