Transient suppressor
AssigneeRCA Corporation
InventorAdel Abdel Aziz Ahmed
Life of this patent
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Abstract
A diode OR gate permits trigger circuits of an array of SCR's to share the same integrating capacitor for suppression of short-lived transients, which might otherwise cause false triggering of the SCR's. The SCR's are switching and latching elements in a telephone cross-point switch array.
Claims7
In a cross-point switch array with a plurality of four-layer devices having their anode-to-cathode paths connected as switching and latching elements between COLUMN and ROW busses and having their respective gate electrodes connected to receive COMMAND pulses of current from respective COMMAND signal lines for triggering their respective anode-to-cathode paths into conduction, triggering circuitry immune to false triggering brought about by transient pulses of shorter duration than said COMMAND pulses, said triggering circuitry comprising:
- a plurality, N in number, of switchable current sources each for being activated by a COMMAND or transient pulse applied thereto from a respective COMMAND signal line;
- a diode OR gate having a plurality, N in number, of input terminals, each connected to a separate one of said switchable current sources, and having an output terminal;
- a capacitance connected between said OR gate output terminal and a point of potential to which the cathodes of said four layer devices are referred, for integrating said transient pulses;
- and
- a plurality, N in number, of threshold potential breakdown devices, each connected between a respective one of said OR gate input terminals and the gate electrode of a respective one of said four-layer devices, their threshold potentials for breakdown being chosen sufficiently low that COMMAND pulses as integrated by said capacitance are large enough to overcome these threshold potentials and being chosen sufficiently high that transient pulses as integrated by said capacitance are too small to overcome these threshold potentials.
The combination of:
- an array of semiconductor controlled rectifiers, each having a conduction path and a gate electrode for controlling conduction through said path;
- a plurality of control circuits, one for each gate controlled rectifier, each including an input terminal to which a COMMAND pulse may be applied, a current source, a normally open switch between that source and the gate electrode of its gate controlled rectifier, and means responsive to said COMMAND pulse for closing the switch of that circuit;
- integrating means for substantially attenuating pulses of shorter duration than one of said COMMAND pulses;
- and
- selective switching means responsive to pulses appearing at each of said input terminals for selectively applying said integrating means to the one of said control circuits having the input terminal on which the largest pulse appears to reduce the sensitivity of that control circuit to such pulse if it be of said shorter duration.
In combination:
- an array of electronic switch devices, each having an input circuit and an output circuit, the output circuit of each electronic switch device having a relatively conductive state and a relatively non-conductive state depending upon whether a control potential appearing at the input circuit of that electronic switch device is above or below a threshold value;
- means for recurrently applying a COMMAND current pulse to a selected one of the input circuits of said electronic switch devices to cause the potential thereacross to exceed said threshold value;
- a plurality of unilaterally conductive devices, each of said unilaterally conductive devices exhibiting relatively easy current conduction from an electrode thereof to a common circuit node and each connected at its said electrode to a different one of the input circuits of said electronic switch devices;
- a capacitance between said common circuit node and a reference potential, said capacitance being of a value to integrate any transient current pulse of shorter duration than said COMMAND pulse which transient current pulse is undesirably coupled to the input circuit of any one of said electronic switch devices and tends to cause the potential across the input circuit of said any one of said electronic switch devices to exceed the potential then present across the input circuit of each other of said electronic switch devices, whereby the likelihood of such shorter duration pulse causing a control potential larger than said threshold value is substantially diminished.
In integrated circuitry built upon a common substrate and having a plurality of conductors for parallelly applied pulse signals, a transient suppressor comprising:
- a plurality of lateral structure transistors having joined bases and joined collectors, said transistors having respective emitter electrodes connected to respective ones of said conductors where transient current pulses may occur which transient pulses are short-lived as compared to said pulse signals and the combined base-to-substrate capacitances of the transistors being free to integrate such transient current pulses and thereby reduce their amplitudes relative to the amplitudes of said pulse signals.
In integrated circuitry built upon a common substrate and having a plurality of conductors for parallelly applied pulse signals, a transient suppressor comprising:
- a plurality of transistors having joined base regions and joined collector regions, one type of said regions being disposed upon said substrate and having the other type of regions disposed therewithin, said transistors having respective emitter regions disposed in their base regions to form base-emitter junctions, which emitter regions are ohmically contacted and connected to respective ones of said plurality of conductors where transient pulses short lived as compared to said pulse signals may occur, said base-emitter junctions providing a diode OR gate for selectively connecting such of said plurality of conductors upon which a pulse occurs to the combined base-to-substrate and collector-to-substrate capacitances of said transistors.
Dependencies are inferred from the claim text.