Dial pulse receiver
AssigneeGTE Automatic Electric (Canada) Limited
InventorJohn A. Gauthier
Life of this patent
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Abstract
A dial pulse receiver having a clock pulse input to a counter and a first and second flip-flop. The outputs of the two flip-flops are coupled to an exclusive OR gate to reset the counter. The counter output and the two outputs of the second flip-flop are coupled to an output gate and latch configuration. The counter is set to enable the latches so only a legitimate dial pulse is recorded.
Claims7
An improved dial pulse receiver for a register and sender arrangement of a communication switching system, said arrangement comprising a plurality of registers and senders, a single clock source producing a single train of clock pulses, and a battery feed device, wherein dial pulses are received by said dial pulse receiver from the battery feed device contact and transmitted from said dial pulse receiver to said registers, said improved dial pulse receiver comprising:
- counter means directly connected to said clock pulses;
- flip-flop means directly connected to said clock pulses and said dial pulses;
- counter reset means coupled to said counter means and to said flip-flop means;
- and
- gate output means coupled to said flip-flop means and to said counter means;
- whereby on receiving a dial pulse the output of said flip-flop means is input to said reset means to reset said counter means and said output being also input to said gate output means, on reaching a predetermined count the output of said counter means enabling said gate output means to transmit a legitimate dial pulse signal if said flip-flop means output is still present at said gate output means or a no legitimate signal being transmitted from said gate output means if said flip-flop means output is no longer present.
Dependencies are inferred from the claim text.