Amplifying circuit for pulse signals
AssigneeFujitsu Limited
InventorsShoichi Kurita, Naohide Sata, Hideki Ogawa, Yoshitaka Hiratsuka
Life of this patent
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Abstract
An amplifying circuit for pulse signals comprises a plurality of delay lines and a plurality of transistor circuits. The base electrode of each transistor is grounded. Each of the delay lines has a delay time of td which can be expressed as tw < 2td, where tw is the duration of the pulses to be amplified. Each of the transistor circuits exhibits a short-circuit impedance for the first incident wave and exhibits the characteristic impedance for the second incident wave of opposite polarity from the first incident wave. The delay lines and the transistor circuits are connected in cascade.
Claims2
An amplifying circuit for pulse signals, comprising
- a pulse signal input terminal for supplying pulse signals having a pulse duration tw;
- a delay line having a predetermined characteristic impedance and a delay time td, the pulse duration tw being less than 2td;
- a transistor having a grounded base electrode, an emitter electrode coupled to the input terminal via the delay line and a collector electrode;
- an impedance having the value of the characteristic impedance of the delay line connected between the emitter and base electrodes of the transistor;
- and
- an output terminal connected to the collector electrode of the transistor.
An amplifying circuit for pulse signals, comprising
- a plurality of delay lines each having a predetermined characteristic impedance and a delay time td;
- a plurality of transistors connected alternately in cascade with the delay lines, each of the transistors having a grounded base electrode, an emitter electrode coupled to the delay line next-preceding it and a collector electrode connected to the delay line next-succeeding it;
- a pulse signal input terminal coupled to the emitter electrode of a first of the plurality of transistors via a first of the plurality of delay lines for supplying pulse signals having a pulse duration tw which is less than 2td;
- a plurality of impedances each having the value of the characteristic impedance of each delay line and each connected between the emitter and base electrodes of a corresponding one of the transistors;
- and
- an output terminal connected to the collector electrode of a last of the plurality of transistors.
Dependencies are inferred from the claim text.