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US 3,940,603 AGranted
Four quadrant multiplying divider using three log circuits
OwnerJohn I. Smithinventor
Life of this patent
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Abstract
Three log circuits are fed by respective x, y and z inputs, along with predetermined interconnections therebetween. The outputs from the log circuits are log z, log (x+z) and log (y+z). These outputs are fed to summing and anti-log circuits to derive the equation (xy)/z + x + y + z. A second summing circuit is provided for substracting the three variables from the resultant output so that (xy)/z is finally derived.
Claims19
An analog multiplying divider for three input variables x, y and z, the multiplying divider comprising:
- first circuit means for performing a log transfer operation upon the variable z;
- second circuit means for performing a log transfer operation upon at least the variable x;
- third circuit means for performing a log transfer operation upon at least the variable y;
- the third circuit means including first means for summing at least log y and the log x output from the second circuit means to form a summation signal which is a function of log x + log y;
- second summing means having inputs thereof connected to the output of the first circuit means and the third circuit means for producing the antilog (log x + log y - log z);
- and
- output means connected to the output of the second summing means for producing (xy)/z at the output thereof.
4 more elements
Dependencies are inferred from the claim text.