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AssigneeTelefonaktiebolaget L M Ericsson
InventorsMartin Wilhelm Ivan Jeppsson, Bruce William Lindstrom, David John Russell
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The present invention relates to an arrangement in a time division multiplex link having at least two pairs of multiplexors and demultiplexors interconnected by separate transmission lines, i.e., redundant transmission systems, with delay, in which time division multiplex channels are formed through the cyclic scanning of the multiplexor inlets and demultiplexor outlets, respectively so that data signals presented to the multiplexor inlets are transferred via the time division multiplex channels in the form of sampling signals to regeneration arrangements connected to the demultiplexor outlets. The sampling signals passed over the separated (redundant) time division multiplex channels are interlaced, i.e., different delays on different transmission lines, thereby producing a resultant sampling density which, when a fault occurs, is reduced by a factor corresponding to the share of the faulty channel in the total number of channels.
In a time division multiplex transmission link for the transfer of binary data from a number of inlets to a corresponding number of outlets, the combination comprising a first multiplexor, a first transmission line and a first multiplexor connecting the inlets to the outlets, a second multiplexor, a second transmission line and a second demultiplexor also connecting the inlets to the outlets, each of said multiplexors generating sampling values resulting from the cyclical scanning of the inlets in response to the receipt of first addressing signals wherein each addressing signal is associated with one of the inlets, each sampling value representing the instantaneous value of the data when an inlet is scanned, means for transferring the sampling values from said multiplexors via the associated transmission line to the associated demultiplexor, means in the demultiplexors for transferring the received sampling values to the outlets in response to the receipt of second addressing signals, wherein each second addressing signal is associated with one of the outlets, a first addressing means for sequentially generating a first set of said first addressing signals for transfer to said first multiplexor, a second addressing means for sequentially generating a second set of said first addressing signals for transfer to said second multiplexor, said first and second sets being interleaved in time, a third addressing means for sequentially generating a first set of said second addressing signals for transfer to said first demultiplexor, a fourth addressing means for sequentially generating a second set of said second addressing signals for transfer to said second demultiplexor, said first and second sets of said second addressing signals being interleaved in time, and synchronizing means for intersynchronizing said addressing means.
Dependencies are inferred from the claim text.