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US 3,939,364 AGranted
Delay line for analogous signals
AssigneeITT Industries, Inc.
InventorsFritz Guenter Adam, Hermannus Schat
Life of this patent
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Abstract
This relates to a bucket-brigade delay line wherein clock frequency dependent modulation of the delayed signal is avoided by inserting at least one inverter stage into the delay line. The output of the inverter stage contains the inverted modulation signal. This signal is then added to the line thereby compensating for the unwanted modulation.
Claims9
A delay line of the type wherein a plurality of stages are coupled together, said delay line having an input to which there is applied a d.c. potential and a signal to be delayed and wherein clock signals are applied to said stages, comprising:
- at least one inverter stage coupled between two adjacent stages of said plurality of stages for inverting the signal potential;
- and
- means for adding the output of said at least one inverter stage to said delay line thereby reducing unwanted modulations with respect to said d.c. input potential.
Dependencies are inferred from the claim text.