Decommutator for extracting zero and one bits from a coded message of duration-modulated pulses
AssigneeCentre National D'Etudes Spatiales
InventorAndre Auguste Ribes
Life of this patent
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Abstract
Decommutator operating on a coded message formed of duration-modulated pulse trains, whereby extraction of the logic signal corresponding to an information is effected by comparing the pulse integrated over the information-characterizing portion of its duration with a reference quantity obtained locally by integrating the pulse over a portion of its duration not characterizing said information, this comparison having for effect to establish the reference voltage threshold of a synchronizing bit that identifies the latter.
Claims6
A decommutator for extracting 0 and 1 bits from duration-modulated pulses of a conventionally coded message in which the initial instants of the pulses are evenly spaced over a time period T and the length of which varies according to the information contained in the pulse, said pulses being first detected before being applied to the decommutator, said decommutator comprising a first integrator and a second integrator, means for applying the detected duration-modulated pulses conjointly to both said integrators, a gated storage element, a multiplying member having a constant multiplication factor, means for connecting the first integrator to the storage element so as to store therein the signals integrated by this first integrator, means for connecting the second integrator to the multiplying member so as to multiply the magnitude of the signals integrated in said second integrator by said constant factor, a comparison means having two inlets and one outlet, means for connecting the storage element and the multiplying member each to one different inlet of the comparison means, and means for controlling the integration intervals of the integrators and the gating of the storage element so that a said pulse is integrated in the first integrator over a period carrying no said information and stored in a succeeding portion of the same period and that said pulse is integrated in the second intergrator over a period carrying said information and multiplied by said factor, whereby the stored integrated signals and the multiplied integrated signals are compared in said comparison means for providing 0 and 1 bits, and means for connecting the outlet of said comparison means to a bit detector for detecting said 0 and 1 bits.
Dependencies are inferred from the claim text.