US 3,938,241 AGranted

Vertical channel junction field-effect transistors and method of manufacture

AssigneeMotorola, Inc.

InventorsWilliam Lloyd George, Robert Guy Hays, Chongkook John Rhee

Life of this patent

Estimating the term…

Loading patent…

Abstract

The disclosed junction field-effect transistor (FET) has a precisely controlled gate configuration which enables either high power operation or high frequency operation or both. The FET is manufactured by steps including the growing of a first epitaxial layer having a predetermined crystallographic orientation on a substrate to form a drain. Next, a first anisotropic etch of the epitaxial layer provides "U"-shaped grooves with flat bottoms, therein through which a gate is diffused having internal side walls of uniform depth that define the source-to-drain channel. A second epitaxial layer is then grown on the surface of the first epitaxial layer and of the gate to provide a source. A second anisotropic etch exposes a portion of the gate, which also forms an etch stop, to facilitate electrical contact thereto. Current flowing through the channel is controlled in response to an input signal applied between the gate and source which adjusts the thickness of a depletion region extending into the channel.

Claims12

Dependent claims

A method of field-effect device comprising:

providing a first layer of semiconductor material of a first conductivity type having a selected crystallographic orientation with respect to a first surface thereof;
selectively etching said first surface of said semiconductor material with an anisotropic etchant to remove some of said semiconductor material virtually only in a direction perpendicular to said first surface to thereby provide a plurality of juxta-positioned grooves having U-shaped cross sections in said semiconductor material, each of said grooves having an exposed bottom surface and exposed side surfaces;
diffusing an impurity of the second conductivity type into said bottom and side surfaces of each of said grooves a predetermined distance to provide a plurality of integral juxta-positioned gate portions of the second conductivity type having bottom and side surfaces, the resulting region of said semiconductor material between said side surfaces of adjacent ones of said gate portions providing a channel;
growing a second layer of semiconductor material of the first conductivity type in said grooves and on said first surface of said first layer of semiconductor material, said second layer being integral with said channel;
and
depositing and patterning conductive material to provide separate electrical connections to said gate and to portions of said first and second semiconductor materials to form gate, drain and source contact areas.

3 more elements

A method of making a vertical channel, field effect transistor comprising:

providing a first layer of heavily doped semiconductor substrate material of a first conductivity type and having a selected crystallographic orientation with respect to a first surface and also having a second surface;
epitaxially growing a second layer of semiconductor material having said first conductivity type and said selected crystallographic orientation on said first surface of said first layer, said second layer having a third surface which is parallel to said first surface of said first layer;
selectively etching said third surface of said second layer with an anisotropic etch which removes virtually only semiconductor material in a direction perpendicular to the plane of said third surface to thereby provide a plurality of grooves each having a U-shaped cross-section in said second layer, each of said grooves having side surfaces extending in a direction substantially perpendicular to said third surface and which are joined together by a bottom surface which is substantially perpendicular to said side surfaces and which forms sharp corners therewith;
rounding said sharp corners of said grooves;
diffusing a plurality of interconnected gate portions of the second conductivity type into said side and bottom surfaces of each of said grooves while simultaneously, selectively retarding diffusion into said surfaces to thereby form gate portions having substantially U-shaped vertical cross-sections;
said gate portions defining channel portions having rectangular vertical cross-sections extending in directions perpendicular to said third surface of said second layer;
epitaxially growing a third layer of semiconductor material of said first conductivity type in said grooves and on the unetched portions of said third surface of said second layer, said third layer having said selected crystallographic orientation and a fourth surface;
and
providing conductive connections to each of said gate and said second surface of said substrate and to said fourth surface of said third layer of semiconductor material to respectively form gate, drain and source contact areas.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 05/482,528Filed 24 Jun 1974 · division
Priority: 24 Oct 1972
Granted: 17 Feb 1976
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10P 95/00
Generic processes or apparatus for manufacture or treatments not covered by the
H10D 30/0515
Of FETs having PN homojunction gates: of vertical FETs having PN homojunction gates
H10D 99/00
Subject matter not provided for in other groups of this subclass
H10P 76/40
Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography: of masks comprising inorganic materials