High speed ECL compatible MOS-Ram

A metal-oxide-silicon, random-access memory which is compatible with emitter-coupled logic and which is deployed on a single substrate comprising:

• a plurality of memory cells for receiving signals;
• a plurality of amplifiers for sensing information in said memory, coupled to said memory cells;
• a first timing generator for receiving an input timing signal and its complement and for generating a first timing signal, said first generator comprising a latched differential amplifier which includes a DC stabilizing loop for controlling DC levels within said amplifier;
• a plurality of memory clock generators for generating a plurality of clock signals, said generators being coupled to said first timing generator;
• and
• a plurality of input buffers for receiving input signals to said memory coupled to said cells;
• whereby said memory generates a first high level clocking signal based on said input timing signal and said high level clocking signal is utilized by the memory to generate other clocking signals for the memory.

A random-access memory deployed on a single silicon substrate comprising:

• a plurality of parallel row lines;
• a plurality of first parallel column lines transverse to said row lines;
• a plurality of second parallel column lines, spaced apart from said first column lines, said second column lines being parallel to said first column lines and transverse to said row lines;
• a first plurality of memory cells for storing information, each of said row lines being coupled to at least one of said first plurality of memory cells, said first plurality of memory cells being coupled to said first column lines;
• a second plurality of memory cells for storing information, said second plurality of memory cells being spaced apart from said first plurality of memory cells, each of said row lines being coupled to at least one of said second plurality of memory cells, said second plurality of memory cells being coupled to said second column lines;
• a plurality of column amplifiers, one of said amplifiers being coupled to one of said column lines such that each of said first and second column lines are coupled to one of said amplifiers;
• a bidirectional input-output line coupled to each of said column amplifiers;
• a sense amplifier coupled to said bidirectional data line for sensing information stored in said cells;
• and
• at least one data input line coupled to said bidirectional data bus line for writing information into said cells;
• whereby a single bidirectional data bus line is utilized to write information into the cells and to read information from said cells.

A decoding system for a memory for decoding an address, which address includes a first part and a second part, said memory including at least a first group of memory cells and a second group of memory cells comprising:

• at least two second level decoding means for decoding said second part of said address, one of said second level decoding means being coupled to said first group of memory cells, the other of said second level decoding means being coupled to said second group of memory cells;
• and
• a first level decoding means for decoding said first part of said address and for selecting one of said first group or second group of memory cells, coupled to said second level decoding circuits;
• whereby said first level decoding means selects one of said first or second groups of memory cells and said second level decoding circuits selects a memory cell within the selected group.