Erasable programmable read-only memory
AssigneeIntel Corporation
InventorsPhillip J. Salsbury, George Perlegos
Life of this patent
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Abstract
A TTL compatible erasable programmable read-only memory (PROM) which uses a single n-channel device having a floating gate for each memory cell. The entire memory including the periphery circuits, are disposed on a silicon substrate. Only a single externally generated high voltage input or "pin" is required for programming.
Claims19
A read-only memory deployed on a doped silicon substrate comprising:
- a first region on said substrate having a higher dopant level than said substrate;
- a plurality of memory cells disposed in said first region, each of said cells including a floating gate for storing charge;
- a plurality of buffers disposed on said substrate, spaced apart from said first region, for communicating signals to said memory cells, each of said buffers including a plurality of field-effect transistors having channels with a first level of dopant and at least one field-effect transistor having a channel with a second level of dopant wherein said saecond level of dopant is higher than said first level of dopant;
- whereby said buffers act as level shifters to permit signals to be readily transmitted to said memory cells.
In a semiconductor memory disposed on a single silicon substrate and which includes a plurality of storage memory cells each of which has a floating gate for storing charge, a sense amplifier coupled to said cells comprising:
- a first branch which includes a first load means and a first transistor, said first transistor being coupled to said storage memory cells;
- a second branch coupled in parallel with said first branch, said second branch including a second load means and a second transistor;
- a memory cell for establishing a reference potential, said memory cell including a floating gate, said memory cell being coupled to said second transistor;
- whereby the reference potential provided by said memory cell establishes a level for said sense amplifier.
A memory circuit having a plurality of floating gate MOS memory cells fabricated on a single silicon substrate comprising:
- means for establishing a predetermined substrate voltage, said substrate voltage being coupled to each of said cells;
- means for establishing an external reference voltage difference from said substrate voltage;
- a a first buffer circuit including a first FET having a channel having a first predetermined dopant level, said first FET being biased with respect to said external reference voltage;
- a level shifter having its input coupled to said first buffer circuit, said level shifter including a second FET having a channel having a second predetermined dopant level higher than said first predetermined dopant level, and a third FET, series-coupled to said second FET, having a channel having said first predetermined dopant level, said level shifter providing its output from said third FET;
- a second buffer circuit coupled to the output of said level shifter, including a fourth FET having a channel having said first predetermined dopant level series-coupled to a fifth FET having a channel having said second predetermined dopant level, said second buffer circuit providing its output from said fifth FET said fifth FET being biased with respect to said substrate voltage.
Dependencies are inferred from the claim text.