Input/output connection arrangement for microprogrammable computer

Abstract

A microprogrammable data processor comprising a generalized three-bus archictecture wherein the functional processing elements are connected between the busses by means of tri-state logic elements which allow the elements to selectively drive, receive from, or present a high impedance to the busses under control of a microprogram. The device includes an input-output system in which the input/output device may have access to all three busses, two for data and for address inputs and the third for receiving output data. The busses may be multifunction busses for carrying either data or address signals. The device utilizes a single phase clock and performs operations in a highly parallel manner. TABLE OF CONTENTS Abstract of the Disclosure Background of the Invention Field of the Invention Description of the Prior Art Summary of the Invention Brief Description of the Drawings Detailed Description of a Preferred Embodiment System Organization Instruction Flow Data Flow Arithmetic and Logic Unit (ALU) General Registers Status Input/Output Scratch Pads/Main Memory Translator Maintenance Control Panel Information Flow: Summary Interrupt Flow Microinstruction Repertoire Single Purpose Micro Fields Multiple Purpose Fields Word/Byte Operation Set/Reset/Test A Bit Addressing and Branching Sample Microprogram System Input/Output I/o interrupt

Dependencies are inferred from the claim text.