US 3,938,096 A · Apparatus for developing an address of a segment within main memory and an absolute address of an operand within the segment

Abstract

Computer addressing hardware and a method of address development which utilizes the concept of a segment as the unit of addressability is disclosed. The fundamental vehicle for addressing is the segment wherein an address space is defined for a process and is included as part of the controlled information of the logical processor (the collection of hardware resources and control information necessary for the execution of a process.) The address space defines a predetermined number of different segments in which instructions can access operands. Within a segment, access is by relative location to the beginning of the segment, and is computed during address development. Any attempt to access information beyond the upper bound of the segment is detected by hardware and an exception condition occurs. An instruction may access an operand either directly or indirectly via a data descriptor, wherein an address syllable in the instruction is used for reference, and specifies whether reference is direct or indirection is to be preferred. The address syllable specifies a base register which defines the segment to be referenced and an offset within the segment. The address syllable also contains a displacement from this defined base. Address development hardware obtains the absolute address of the beginning of the segment, adds to this; the offset defined in the base registers, the displacement defined by the instructions, and if required the contents of an index register. This summation produces the required absolute address.

Claims8

Dependent claims

An apparatus for developing an absolute address for a selected operand within a selected one of a plurality of variable size segments within a memory space, said apparatus comprising:

a. first means for storing a plurality of first addresses for identifying and locating said variable size segments within said memory space;
b. second means for storing a plurality of second addresses for identifying said variable size segments and for providing an address of a first byte of said selected operand within said variable size segments;
c. third means, coupled to said second means, for selecting one of said second addresses;
d. fourth means, in said first means and coupled to said second and third means, for matching the variable segment of said selected one of said second addresses with one of the variable segments of said first addresses;
e. fifth means, coupled to said first, second and third means and responsive to said fourth means, for adding said selected one of said second addresses to one of said first addresses whose segment matches the segment of said selected one of said second addresses;
and,
f. sixth means, coupled to said fifth means, for storing a third address of said selected operand said third address being the address of a selected byte in said operand relative to the first byte, and whereby said fifth means adds said third address to said first and second addresses to generate the absolute address of a byte within said selected operand.

4 more elements

An apparatus for developing an absolute address for a selected operand within a selected one of a plurality of variable size segments within the memory space, said apparatus comprising:

a. first means for storing a plurality of segment descriptors, one each of said segment descriptors associated with one each of preselected ones of said plurality of variable size segments, each of said segment descriptors containing a base address of its associated segment within said memory space and said first means further containing a maximum address limit field for defining a maximum address limit of a segment associated with a segment descriptor;
b. second means, coupled to said first means, for storing a plurality of segment numbers, one each of said segment numbers corresponding with one each of said preselected one of said segments having an associated segment descriptor stored in said first means;
c. third means for storing the segment number of said selected one of said plurality of variable size segments located in said memory space;
d. fourth means, in said second means and coupled to said third means, for matching said segment number in said third means with one of said plurality of segment numbers in said second means;
e. fifth means for storing an offset address of said selected operand within said selected segment in said memory address space said offset address being the location of a first byte of said operand within said selective segment;
f. sixth means, coupled to said first and fourth means, for storing the base address of a selected one of said preselected segments, said base address located in a descriptor stored in said first means, said descriptor's associated segment number having been matched with one of said segment numbers stored in said third means;
g. seventh means, coupled to said fifth and sixth means and responsive to said fourth means for adding said offset address in said fifth means with said base address in said sixth means, whereby the absolute address of said selected operand is generated;
and,
h. limit means, coupled to said first and seventh means for determining that the resulting address from said seventh means is less than the maximum address limit in said first means.

6 more elements

Dependencies are inferred from the claim text.

Apparatus for developing an address of a segment within main memory and an absolute address of an operand within the segment

Life of this patent

Apparatus for developing an address of a segment within main memory and an absolute address of an operand within the segment

Life of this patent

Abstract

Claims8