Computing system bus

In a computing system which includes a central processing unit in combination with a plurality of external memory units, wherein said processing unit includes, in spaced apart regions on a single chip, a parallel arithmetic logic unit in a first region, a random access memory unit in a second region, an instruction register in a third region, and a control circuitry in a fourth region, interconnected on said chip in a fifth region by a common parallel internal bus, logic circuitry for precharging said internal bus prior to entering data on said bus, and for selectively providing output signals corresponding to data stored on said bus, comprising in combination:

• a. a first logic gate having an output terminal connected to said bus and first and second input terminals for receiving logic signals, the logic level of said output terminal selectively variable responsive to the logic level of signals at said input terminals;
• b. first and second transfer gates connected to series coupling said bus to circuit ground, respectively having control electrodes, the juncture between said gates defining a node for receiving input data and for providing output data, said first transfer gate being connected to said first input terminal and said second transfer gate being connected to circuit ground, said first transfer gate having its control electrode connected to a first clock phase of a multi-phase clock system whereby responsive to said first clock phase, input data present at said node is transferred to said first terminal of said first logic gate;
• c. a third transfer gate for coupling a first voltage source to said bus during said first phase of said clock system to charge said bus to a reference potential;
• d. logic means coupled to said second input terminal of said first logic gate responsive to said first phase of said clock system and a first control signal for selectively discharging said bus system;
• and
• e. a second logic gate having an output connected to said control electrode of said second transfer gate, having a first input connected to said bus and a second input disposed for receiving a second control signal responsive to which said second transfer gate is selectively shunted to ground, thereby providing an output signal at said node corresponding to data stored on said bus.

In a calculating system which includes, on a single chip, a central processing unit having an arithmetic logic unit, a random access memory unit, an instruction register, and control circuitry in spaced apart regions on said chip and interconnected by a common parallel bus system on said chip, means for precharging said bus system during a first phase of a multi-phase clock system and selectively discharging said bus system during an interval between said first phase and a subsequent second phase of said clock system responsive to enable signals generated by said control circuitry, comprising in combination:

• a. first gating means for coupling a voltage source to said bus system during said first phase of said multi-phase clock system to charge said bus to a reference potential;
• b. a first logic gate having an output terminal connected to said bus, and having first and second input terminals for receiving logic signals, the logic level of said output terminal selectively variable responsive to the logic level of signals present at said input terminals;
• c. second gating means connected to said first input terminal of said first logic gate for applying an input signal thereto corresponding to the desired logic level of said bus;
• and
• d. a second logic gate having an output connected to said second input terminal of said first logic gate, said second logic gate having a first input that is said first phase of said clock signal, and a second input that is a control signal for providing an enable signal to said first gating means for selectively discharging said bus.

In a data processing system wherein binary data is transmitted from a first data processing station to a second spaced data processing station over a common parallel bus system, responsive to first and second clock signals from a multiphase clock source, the combination comprising:

• a. means connected to said first station for selectively generating currents on respective lines of said bus system responsive to said first clock signal, said currents corresponding to output data which is to be transmitted therefrom;
• b. differential amplifier means coupled to said bus system for detecting said currents and providing output signals responsive thereto;
• c. logic means responsive to said first clock signal for receiving said output signals and providing logic output signals corresponding thereto;
• d. voltage generating means connected to said bus for generating voltages thereon;
• and
• e. gating means connecting said voltage generating means and said logic means, said gating means having a control electrode for receiving said second clock signal whereby responsive thereto said logic output signals are connected to said voltage generating means enabling transmission of voltage signals corresponding to said output data to said second processing station.