Error detection apparatus for verifying binary coded constants

Error detection apparatus for use in a peripheral controller which controls a plurality of magnetic tape devices for checking speed constants specifying a plurality of different tape velocities, said error detection apparatus comprising:

• a register coupled to receive a speed constant coded to designate a specified one of said plurality of different tape velocities;
• decoder means having n input terminals and at least 2.sup.n output terminals, said n input terminals being connected to said register for receiving signals representative of said speed constant;
• circuit selection means having a predetermined number of input terminals and ouptut terminals, said input terminals being connected only to those output terminals producing predetermined signals indicative of having decoded a valid speed constant;
• and,
• check logic circuit means having at least one output terminal and a plurality of input terminals connected to said predetermined number of output terminals, said logic circuit means being operative to generate an output signal at said output terminal indicative of a valid code and no faults in said decoder circuit and inhibits generation of said output signal when said decoder generates none and more than one predetermined output signal on said 2.sup.n output terminals indicative of decoding an invalid speed code.

An error detector circuit for signaling receipt of valid binary coded signals, said detector circuit comprising:

• a binary to non binary decoder circuit means having n input terminals and 2.sup.n output terminals;
• a predetermined number of conductors connected at one end to less than 2.sup.n output terminals;
• and,
• a parity check circuit having a predetermined number of input terminals connected to the other end of said predetermined number of conductors, said parity circuit being operative to generate an output signal only when said binary to non binary decoder circuit forces only one of said predetermined number of conductors to a predetermined state indicating that said binary code is valid and that said decoder circuit is operating without fault.