Circuitry for preventing the use of erroneous data
OwnerRobert T. Kirkinventor
Life of this patent
Estimating the term…
Abstract
A transceiver for computer controlled stacker cranes comprising an interface which controls the voltage level of incoming and outgoing serial signals, a sampling circuit and a voting circuit which together prevents transmission of transient or improper signals received from the interface, shift registers converting incoming serial data to parallel data and also converting stored parallel data to outgoing serial data, a temporary storage memory which holds parallel data received from the shift registers until commanded by timing signals to output said data, an end of transmission decoder which senses the end of a data message and triggers certain timing signals, timing circuitry for clocking transfer of data to and from said memory, and circuitry for preventing simultaneous transmission and reception of data.
Claims2
Circuitry for preventing the use of erroneous data in a transceiver for controlling computerized stacker cranes comprising:
- means receiving serial incoming signals comprising data bits and control bits including a lead control bit;
- memory means for storing at least some of said control bits and all said data bits;
- voting circuitry in communication with said memory means and to which said data bits and at least some of the control bits are communicated, said voting circuitry comprising signal comparator means;
- sampling circuitry in communication with the voting circuitry and to which the lead control bit is communicated, said sampling circuitry comprising means subdividing the lead control bit into sub-parts, delay sampling means for examining intermediate sub-parts of the lead control bit and clocking the voting circuitry when the state of said intermediate sub-parts comprise a predetermined state, and means for thereafter clocking the voting circuitry causing the signal comparator means to vote on all said data bits and at least some of the control bits, whereby approved bits are communicated to said memory means, and means turning off the voting circuitry when the state of said lead control bit is other than said predetermined state.
Dependencies are inferred from the claim text.