Digital demodulator for phase-modulated waveforms

Apparatus for demodulating a received wave having phase-shifts of +45.degree., +1350.degree., +.sub.".degree. and +315.degree. between successive signalling intervals, the phase shifts encoding four dibit combinations, which comprises:

• a timing generator;
• means for synchronizing the timing generator with the received wave;
• means for generating a squared version of the received wave;
• a shift register having a plurality of stages for serially storing samples at a first periodic rate of the squared wave encompassing a current signalling interval and at least a portion of a previous signalling interval;
• a first exclusive-OR gate associated with the first and the second of the dibit combinations for comparing samples stored in two stages selected to encompass the span between like-phased samples of the waves from the previous and current signalling intervals;
• a first counter associated with the first dibit combination;
• a second counter associated with the second dibit combination;
• means controlled by the timing generator and the first exclusive-OR gate for incrementing at the first periodic rate during a mid-portion of each signalling interval, the first counter when the output of the first exclusive-OR gate indicates that the samples compared thereby agree, and the second counter when the output of the first exclusive-OR gate indicates that the samples compared thereby differ;
• a second exclusive-OR gate associated with the third and the fourth of the dibit combinations for comparing samples stored in two stages selected to encompass the span between like-phased samples of the waves from the previous and current signalling intervals;
• a third counter associated with the third dibit combination;
• a fourth counter associated with the fourth dibit combination;
• means controlled by the timing generator and the second exclusive-OR gate for periodically incrementing at the first periodic rate, during a mid-portion of each signalling interval, the third counter when the output of the second exclusive-OR gate indicates that the samples compared thereby agree, and the fourth counter when the output of the second exclusive-OR gate indicates that the samples compared thereby differ;
• four output gates, one of the output gates being connected to each counter for sensing when that counter reaches a particular count;
• means controlled by the timing generator and the output gates for simultaneously incrementing the counters at a second periodic rate higher than the first periodic rate during a portion of each signalling interval subsequent to the mid-portion until one of the output gates becomes enabled, thus identifying the data element associated with the enabled output gate as received during the signalling interval;
• and
• means controlled by the timing generator for resetting the counters subsequent to one of the output gates becoming enabled and before the mid-portion of the next signalling interval.

A demodulator for a received wave having phase shifts of +45.degree., +135.degree., +225.degree. and +315.degree. between successive signalling intervals that encode a respective plurality of dibit combinations of the type having:

• a timing generator, means for synchronizing the timing generator with the received wave, means for generating a squared version of the received wave, a shift register for storing periodic samples of the squared wave for a period encompassing a current signalling interval and at least a portion of a previous signalling interval, means responsive to selected samples from the shift register and controlled by the timing generator for decoding data elements received during each signalling interval and for loading the received data elements into an output register, characterized in that:
• the means for decoding data elements comprises a pair of exclusive-OR gates connected to selected stages of the shift register for comparing pairs of samples from the shift register;
• a first filter connected to the output of the first one of the exclusive-OR gates to eliminate shortterm transitions in the output signal thereof, the first exclusive-OR gate being connected to compare the first sample with the second sample delayed by one signalling interval with respect to the first sample;
• a second filter connected to the output of the second one of the exclusive-OR gates to eliminate short-term transitions in the output signal thereof, the second exclusive-OR gate being connected to compare the first sample with the third sample removed drom the second sample by an interval occupied by a 90.degree. segment of the received wave, the short-term transitions eliminated by the first and second filters having a duration shorter than the interval occupied by a 90.degree. segment of the received wave;
• and
• means controlled by the timing generator for loading the output of the first filter directly into one stage of the output register to represent one bit of the received dibit combination and for loading the output of the second filter directly into another stage of the output register to represent the other bit of the received dibit combination.