Method and apparatus for packed BCD sign arithmetic employing a two's complement binary adder

A data processing system storing a BCD encoded addend A.sub.d and a BCD encoded auguend A.sub.v which are operated upon in low to high order information bytes to form a decimal arithmetic sum S.sub.a, where each byte includes least and most significant decimal digits each encoded as four BCD bits, said system comprising,

• an eight bit adder having first and second inputs for the least and most significant BCD digits to be added, said adder having fourth and eighth bit carry outputs and a blocking input for blocking the fourth carry input to the fifth bit,
• an input control unit for directing data to said adder inputs and providing a predetermined translation value and plural predetermined adjust values,
• a plurality of registers for storing operands including said addend A.sub.d and said auguend A.sub.v,
• a carry storage unit for storing the adder carry outputs,
• control means for controlling the processing of operands,
• means, responsive to said control means, for gating the auguend from said registers to the first input of said adder and for gating the predetermined operand translation value to the second input of said adder to form a preconditioned auguend sum and connecting said adder to said registers for storing said sum,
• means, responsive to said control means, for gating the preconditioned auguend and the addend from the registers and the carry from the carry storage to the first and second inputs of said adder to form a sum and connecting the adder output to said registers for storing said sum, and simultaneously storing the adder carry outputs in said carry storage,
• means, responsive to said control means, for gating to said input control unit the contents of said carry storage and for generating predetermined adjust values in response thereto,
• means, responsive to said control means, for gating the initial sum from said registers and the adjust values to the first and second inputs of said adder to form an adjusted sum, and gating said sum to said registers for storing said sum.

A data processing system storing a BCD encoded subtrahend S.sub.d and a BCD encoded minuend S.sub.m which are operated upon in low to high order information bytes to form a decimal arithmetic difference D, where each byte includes least and most significant decimal digits each encoded as four BCD bits, said system comprising,

• an eight bit adder for adding and two's complementing operands having first and second inputs for the least and most significant BCD digits to be added, said adder having fourth and eighth bit carry outputs and a blocking input for blocking the fourth carry input to the fifth bit,
• an input control unit for directing data to said adder inputs,
• a plurality of registers for storing operands including said subtrahend S.sub.d and said minuend S.sub.m,
• a carry storage unit for storing the adder carry outputs,
• control means for controlling the processing of operands,
• means, responsive to said control means, for gating said byte of said subtrahend S.sub.d from said registers to the first input of said adder and for two's complementing said byte of S.sub.d,
• means, responsive to said control means, for gating said byte of said minuend S.sub.m from said registers to the second input of said adder to form a sum, by addition of the two's complement of said byte S.sub.d and said byte of said minuend S.sub.m, and connecting the adder output to said registers for storing said sum, and simultaneously storing the adder carry outputs in said carry storage,
• means, responsive to said control means, for gating to said input control unit the contents of said carry storage and for generating predetermined adjust values in response thereto,
• means, responsive to said control means, for gating the initial sum from said registers and the adjust values to the first and second inputs of said adder to form an adjusted sum, and gating said sum to said registers for storing said sum, said adjusted sum forming the difference D.

A method for arithmetic operation in a data processing system storing a BCD encoded number N and a BCD encoded number P which are operated upon in low to high order information bytes to form a decimal arithmetic sum and a decimal arithmetic difference where each byte includes least and most significant decimal digits each encoded as four BCD bits, said system having a first unit having carry outputs for adding and for two's complementing operands, having an input control unit for directing data to said first unit and providing a predetermined translation value and plural predetermined adjust values, having a plurality of registers for storing operands, having control means for controlling the processing of operands, having a carry storage unit for storing the adder carry outputs, the steps comprising,

• gating an information byte of number N from said register means to said adder,
• gating, if the operands are to be added, a predetermined operand translation value to said adder, adding said byte of N and said translation value to form a preconditioned sum and storing said sum in said registers,
• gating, if the operands are to be subtracted, said byte of N to said adder, two's complementing said byte of N and storing the result thereof,
• gating said byte of N and byte of P from said registers and said carry storage to the inputs of said adder, adding said inputs to form an initial binary sum and storing said initial sum in said register means, and simultaneously storing the adder carry outputs in said carry storage,
• gating the contents of said carry storage to said control unit, forming an adjust value in a predetermined manner and storing said value in said register means,
• gating the initial sum from said registers and adjust value from storage to said adder inputs, adding said initial sum and said adjust value to form an adjusted sum, and storing said sum in said register means.

A method for arithmetic operation in a data processing system storing a BCD encoded number N and a BCD encoded number P which are operated upon in low to high order information bytes to form a decimal arithmetic sum and a decimal arithmetic difference where each byte includes least and most significant decimal digits each encoded as four BCD bits, said system having a first unit having carry outputs for adding and for two's complementing operands, having an input control unit for directing data to said first unit and providing a predetermined translation value and plural predetermined adjust values, having a plurality of registers for storing operands, having control means for controlling the processing of operands, having a carry storage unit for storing the adder carry outputs, the steps comprising,

• if the operands are to be added, adding said byte of N and a predetermined operand translation value to form a preconditioned sum and storing said sum in said registers,
• if the operands are to be subtracted, two's complementing said byte of N,
• adding said byte of N and byte of P and said carry outputs to form an initial binary sum and storing said initial sum in said register means, and simultaneously storing the adder carry outputs in said carry storage,
• forming an adjust value in a predetermined manner and storing said value in said register means, and adding said initial sum and said adjust value to form an adjusted sum, and storing said sum in said register means.