Fault detection process and system for a time-division switching network
AssigneeInternational Standard Electric Corporation
InventorJean Pierre Le Pabic
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AssigneeInternational Standard Electric Corporation
InventorJean Pierre Le Pabic
Estimating the term…
A fault detection process and system is disclosed for large multistage time division-space division-time division switching networks. In the input time-division switch an origin bit is simultaneously transmitted with each sample to the related output channel of the output time division switch. The origin bit is produced by modulating a selected bit of the input channel address by an associated sample parity bit. In the output switch the modulated origin bit is demodulated by the received sample parity bit. This demodulated origin bit is compared with the corresponding bit of the input channel address which has been stored in a memory of the output switch under control of the network computer unit. In addition, means are provided for taking into account input delay, transmission delay and output delay.
A fault detection process for detecting faults occurring in a time-division switching network comprising the steps of
A fault detection system for a time-division switching network comprising:
Dependencies are inferred from the claim text.