Offset voltage correction circuit for multiple video channel imager

An imaging system comprising

• a. a semiconductor substrate having a major surface;
• b. a first and a second plurality of conductive plates, each overlying and in an insulated relationship to said major surface thereby to form first and second pluralities of MIS capacitors, respectively, each of said first MIS capacitors being adjavent and coupled to a respective one of said second MIS capacitors to form a plurality of pairs of MIS capacitors, said pairs arranged in a matrix of rows and columns;
• c. a plurality of column conductor lines arranged in plurality of consecutively numbered sets, each set having an equal number of consecutively numbered lines, each line connected to the second plates of each column, respectively;
• d. a plurality of column switches;
• e. a plurality of consecutively numbered terminals equal in number to the number of sets, each line connected through a respective one of said column switches to the terminal corresponding in number to the set number of said line;
• f. a plurality of row conductor lines, each row line connected to said first plates of each row, respectively;
• g. a first voltage means for providing a first voltage between said row conductor lines and said substrate to deplete respective first portions of said substrate lying thereunder of majority charge carriers;
• h. a second voltage means connected in circuit between each set of said column conductor lines and said substrate for providing a second voltage between said column conductor lines and said substrate to deplete respective second portions of said substrate lying thereunder of majority charge carriers, said substrate maintained at a fixed potential in relation to said second voltage means;
• i. means for exposing said substrate to radiation whereby charge is stored in said first and second portions of said substrate;
• j. first means for collapsing and reestablishing said first voltage on each of said row conductor lines in sequence during a respective period of time;
• k. means for actuating the column switches of each set during a respective second period of time whereby the column lines of each set are connected in turn to said terminals;
• l. a plurality of circuit means each connected between a respective one of said terminals and said second voltage means;
• m. second means for collapsing and reestablishing said second voltage on said terminals during said second periods of time, whereby charge stored in the second semiconductor capacitors of each set is simultaneously driven out of said respective second capacitors and currents are caused to flow simultaneously in each of said circuit means;
• n. each of said circuit means including means for integrating each of said current flows with respect to time to provide a respective output of sequentially occurring levels of voltage;
• o. a plurality video channel circuit means each connected to respective ones of said integrating means for providing a plurality of video channel outputs;
• p. correction circuit means, connected to said plurality of video channel circuit means for generating a correction signal to cancel a D.C. offset voltage between said video channel outputs.