Digital phase-lock loop systems for phase processing of signals
AssigneeThe Charles Stark Draper Laboratory, Inc.
InventorsDuncan B. Cox, Jr., William H. Lee
Life of this patent
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Abstract
A digital phase-locked loop in which an error signal representing the difference between the phases of an input signal and an output signal is converted to a digital signal having a time-varying value. A programmable divider means is provided to produce a pulse control signal having a frequency which varies in accordance with the time-varying value of the digital signal. The pulse control signal controls the number of pulses which are deleted from a reference clock signal to produce an intermediate signal which in turn is fed to a feedback counter for producing the output signal, the phase of which depends on the number of deleted pulses, so that the phase of the output signal effectively follows the phase of the input signal.
Claims25
A phase processing system comprising means responsive to an input signal having a first phase and further responsive to an output signal having a second phase for producing an error signal representing the phase difference between said first and second phases;
- means for producing a reference clock signal having a fixed clock frequency;
- means responsive to said clock signal and to said error signal for converting said error signal to a digital signal having a value representing said error signal;
- means responsive to said clock signal and to said digital signal for producing a pulse control signal having a frequency which varies in accordance with the time-varying value of said digital signal;
- means responsive to said pulse control signal and to said reference pulse clock signal for controllably changing the number of pulses from said reference pulse clock signal in response to said pulse control signal to produce an intermediate clock signal;
- means responsive to said intermediate clock signal for producing said output signal, the phase of which depends on said controlled number of pulses.
A phase processing system comprising
- means responsive to an input signal having a first phase and further responsive to an output signal having a second phase for producing an error signal representing the phase difference between said first and second phase;
- means for producing a pulse clock signal having a fixed clock frequency;
- means responsive to said pulse clock signal for producing a first reference signal having a first frequency proportional to that of said pulse clock signal;
- means responsive to said first reference signal and to said error signal for converting said error signal to a digital signal having a digital value representing the value of said error signal;
- means responsive to said pulse clock signal for producing a second reference signal having a second frequency proportional to that of said pulse clock signal;
- means responsive to said second reference signal and to said digital signal for producing a pulse control signal having a frequency equal to the frequency of said second reference signal divided by a value representing the sum of a fixed value and said digital value;
- means responsive to said pulse clock signal for producing a third reference signal having a third frequency proportional to that of said pulse clock signal;
- means responsive to said third reference signal and to said pulse control signal for controllably changing the number of pulses from said third reference signal in response to said pulse control signal to produce an intermediate clock signal;
- means responsive to said intermediate clock signal for producing said output signal the phase of which depends on said controlled number of pulses.
A phase-processing system comprising
- means responsive to an input signal having a first phase and further responsive to an output signal having a second phase for producing an error signal representing the phase difference between said first and second phases;
- means for producing a pulse clock signal having a fixed clock frequency;
- means responsive to said pulse clock signal for producing a first reference signal having a first frequency proportional to that of said pulse clock signal;
- means responsive to said first reference signal and to said error signal for converting said error signal to a digital signal having a digital value representing the value of said error signal;
- means responsive to said pulse clock signal for producing a second reference signal having a second frequency proportional to that of said pulse clock signal;
- and
- means responsive to said second reference signal and to said digital signal for producing said output signal having a frequency that varies in accordance with the time-varying value of said digital signal.
Dependencies are inferred from the claim text.