US 3,935,438 A · Decimal adder

Abstract

A decimal adder has plural arithmetic stages, each for generating one new bcd digit, and a controller for all stages. Each stage has three, four-stage binary adders one as input receiver for one input bcd digit, one main adder and one as output corrector. The input adder adds six to that one input bcd digit for a true addition, the output adder adds ten (or subtracts 6) selectively under various conditions. The second bcd digit for a stage is either passed directly to the main adder or its 16- complement; the second input for the main adder is the output of the input adder. The output of the main adder is either fed directly or its 16- complement to the output adder. The controller controls selectivity of operation of input adders and complement input formation in all stages in response to equal or unequal sign bits. The controller controls formation of complement of the output of all main adders when the overall result is negative but not because both sign bits are negative. The add-ten of the output adder in each stage is controlled on the basis of the carry bit generated by the main adder in the particular stage and in response to the sign of the overall result. The carry in - carry out chain from stage to stage is closed in a loop through the controller, generating a carry-in bit for the subtract operation when the resultant sign is positive. This loop represents the sign of overall result in case of subtraction.

Claims23

Dependent claims

A decimal parallel adder comprising:

a plurality of arithmetic stages, one each for forming a new decimal digit, each such stage having a first binary adder for receiving signals representing a first and a second digit to be added;
circuit means in each said stage connected for feeding said signals to said adder and selectively and mutually exclusively providing the bit by bit complement of one digit and adding a particular number to one of the two digits;
a second adder in each said stage connected so that its output provides said new decimal digit;
second circuit means in each said stage for selectively passing direct or complement of the output of said first adder as one input to said second adder;
third circuit means in each said stage for selectively passing or suppressing signals representing a fixed number to said second adder and equivalent to a subtraction of the number as added by operation of the first circuit means;
circuit means for connecting the carry output of each first adder to the carry input of the first adder of the stage forming the next higer significant decimal digit;
and
a controller common to all stages and connected to be responsive to the sign bits of numbers whose digits are fed to said stages and providing control signals for control of the selectivity of said first circuit means and further providing other control signals for control of the selectivity of said second circuit means, the controller additionally providing a sign bit for the number as assembled by operation of all said stages.

5 more elements

A decimal adder with one stage for each bcd digit to be generated from the bcd digit of two numbers applied to the decimal adder for the generation of a resultant number in accordance with a specified arithmetic operation, comprising:

a controller responsive to the sign bits of the numbers fed to the adder and generating a sign bit for the resultant number;
a binary adder in each stage for adding two bcd numbers and a carry bit when received to each other and providing the sum of its inputs as well as carry bit;
an input circuit for the adder in each stage receiving two bcd numbers and feeding them as two input numbers to said adder, and including means for generating selectively the 16-complement of one of the numbers;
a correcting stage in each arithmetic stage and connected for providing for the selective addition of ten to a number received and generating a bcd digit as output digit of the arithmetic stage, the output digit being a digit of the resultant number;
first circuit means in each arithmetic stage and being selectively operated for passing the output or its 16-complement of the adder to said correcting stage as number received;
second circuit means in the stage for controlling the selectivity of the selective addition in the correcting stage in response to the carry generated by the adder and in further response to the signs of the numbers as received by the controller;
third circuit means including the controller connected for controlling the selectivity of the first circuit means in response to the generation of the resultant sign bit from unequal signs bits as received by the controller;
and
further circuit means in the controller for controlling the input circuit means of all stages in response to in-equality of the sign bits of the numbers received the controller.

6 more elements

A decimal parallel adder comprising a plurality of arithmetic stages, one stage each for forming a new decimal digit, comprising:

first circuit means in each stage connected to receive signals representing first and second bcd digits and modifying the signals by selectively providing operation representing adding six to one of the digits or forming the difference between fifteen and one of the digits;
a first, four stage binary adder in each stage with carry input and carry output, the carry output of the first adder in a stage being connected to the carry input of the first adder in the stage forming a digit of next higher significance, the first adder in each stage connected to receive from the first circuit means of the stage signals representing the two digits as selectively modified by the first circuit means and providing signals representing the sum modulo sixteen thereof;
second circuit means in each stage connected to selectively produce, as an output, signals representing fifteen minus the sum as produced by the first adder or pass the signals representing the sum unmodified as output;
a second adder connected to receive said output of said second circuit means;
third circuit means in each stage connected to feed signals representing the number ten to said second adder;
and
control means connected to be responsive of sign bits for controlling the selectivity of said first, and second and circuit means in response to the sign bits received and in further response of the carry from the stage of highest significance.

4 more elements

Dependencies are inferred from the claim text.

Decimal adder

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Decimal adder

Life of this patent

Abstract

Claims23