Process for the production of a pair of complementary field effect transistors

A process for the production of a pair of complementary field effect transistors on a substrate of insulating material which comprises:

• a. forming a low doped monocrystalline semiconductor layer on the insulating substrate;
• b. forming a gate insulator layer on said semiconductor layer;
• c. forming first and second gate electrodes on said insulating layer;
• d. forming an oxide masking layer over the exposed surface regions of said semiconductor layer and over said electrodes;
• e. etching first and second openings through said masking layer and through said gate insulating layer, said first opening adjoining one side of said first gate electrode and said second opening adjoining one side of said second gate electrode;
• f. effecting a first doping step comprising
• i. diffusing charge carriers of a first type into a first region of said semiconductor layer lying beneath said first opening and beneath a portion of said first gate electrode, and
• ii. diffusing charge carriers of a second type into a second region of said semiconductor layer lying beneath said second opening and beneath a portion of said second gate electrode;
• g. removing all parts of said gate insulating layer apart from the parts located below said gate electrodes;
• and
• h. effecting a second doping step comprising
• i. doping with charge carriers of the second type the semiconductor layer on opposite sides of said first gate electrode while leaving the portion of said first region unchanged below said first gate electrode, and
• ii. doping with charge carriers of the first type the semiconductor layer on opposite sides of said second gate electrode while leaving the portion of said second region unchanged below said second gate electrode;
• whereby the doped semiconductor regions on opposite sides of said first gate electrode provide the source and drain regions of a first Metal Oxide Silicon field effect transistor, and the doped regions on opposite sides of said second gate electrode provide the source and drain regions of a second Metal Oxide Silicon field effect transistor.